Back to results
US 7,003,635 B2Granted
Generalized active inheritance consistency mechanism having linked writes
AssigneeHewlett-Packard Development Company, L.P.
InventorStephen R. Van Doren
Life of this patent
Estimating the term…
Abstract
A system and method provides active inheritance on memory writes such that entities issuing later writes ensure that the effects of earlier writes to the same memory block will be seen. A write chain is preferably formed by storing information and state in miss address file (MAF) entries maintained by the entities. The write chain links the entities requesting write access to the memory block. When the desired memory block becomes available, the information and state stored at the MAF entries is then utilized by each entity in ensuring that all earlier writes are complete before its write is allowed to complete.
Claims18
A method of ensuring data consistency in a computer system having a plurality of data processing entities and a shared memory organized into a plurality of memory blocks, at least some of the data processing entities configured to issue requests for selected memory blocks, the method comprising:
- issuing from a plurality of data processing entities a sequence of writes targeting a given memory block;
- linking the writes to the given memory block into a write chain, the write chain specifying a last data processing entity in the sequence, and being free from having one or more reads targeting the given memory block;
- at each data processing entity in the write chain other than the last data processing entity, storing information that identifies the next data processing entity in the write chain;
- and
- at each data processing entity in the write chain other than the last data processing entity, ensuring that the prior data processing entity completed its write before completing the current write.
2 more elements
A method of ensuring data consistency in a computer system having a plurality of data processing entities and a shared memory organized into a plurality of memory blocks, at least some of the data processing entities configured to issue requests for selected memory blocks, the method comprising:
- issuing from a plurality of data processing entities a sequence of writes targeting a given memory black;
- linking the writes to the given memory block into a write chain, the write chain specifying a last data processing entity in the sequence;
- at each data processing entity in the write chain other than the last date processing entity, storing information that identifies the next data processing entity in the write chain;
- at each data processing entity in the write chain other than the last data processing entity, ensuring that the prior data processing entity completed its write before completing the current write;
- providing a data structure at each data processing entity;
- configuring the data structure at each data processing entity in the write chain other than the last data processing entity to store a pointer to a next data processing entity in the write chain;
- and
- configuring the data structure at each data processing entity in the write chain to indicate:
- an Inval Count corresponding to a number of data processing entities that had a copy of the given memory block at the time the respective data processing entity issued its write, and
- an Invalidate_Acknowledgement (IAck) count corresponding to a number of IAcks received by the respective data processing entity.
7 more elements
A computer system comprising:
- a plurality of data processing entities, at least some of the data processing entities having one or more caches;
- and
- a main memory coupled to the plurality of data processing entities by an interconnect fabric, the main memory organized to store data in terms of memory blocks at least one or more of which are shared by the plurality of data processing entities,
- wherein the data processing entities are configured to:
- issue writes to a given memory block,
- cooperate in the formation of a write chain linking each of the data processing entities that issued a write to the given memory block, the write chain specifying a last data processing entity, and each data processing entity in the write chain, other than the last data processing entity, specifying a next data processing entity in the write chain, and the write chain free from having one or more reads, and
- ensure that a prior data processing entity in the write chain completed its write before completing the respective data processing entity's write.
4 more elements
A computer system comprising:
- a plurality of data processing entities, at least some of the data processing entities having one or more caches;
- and
- a main memory coupled to the plurality of data processing entities by an interconnect fabric, the main memory organized to store data in terms of memory blocks at least one or more of which are shared by the plurality of data processing entities,
- wherein the data processing entities are configured to:
- issue writes to a given memory block,
- cooperate in the formation of a write chain linking each of the data processing entities that issued a write to the given memory block, and
- ensure that a prior data processing entity in the write chain completed its write before completing the respective data processing entity's write
- wherein each data processing entity has a data structure, each data structure configured to have a write pointer field and a write state field,
- wherein the write pointer fields of the data structures at the data processing entities forming the write chain, other than the last data processing entity, store a pointer to a next data processing entity in the write chain
- wherein the data structures are further configured to include
- an Inval Count corresponding to a number of data processing entities that had a copy of the given memory block at the time the respective data processing entity issued its write, and
- an Invalidate_Acknowledgement (IAck) count corresponding to a number of IAcks received by the respective data processing entity.
9 more elements
A computer system comprising:
- a plurality of data processing entities, at least some of the data processing entities having one or more caches;
- a main memory coupled to the plurality of data processing entities by an interconnect fabric, the main memory organized to store data in terms of memory blocks at least one or more of which are shared by the plurality of data processing entities;
- and
- one or more directories for use in maintaining cache coherence of the memory blocks, the one or more directories having an entry for each memory block, each directory entry including an owner field for specifying an owner of the memory block, and a writer field for specifying the last data processing entity to have written the memory block back to the main memory,
- wherein the data processing entities are configured to:
- issue writes to a given memory block,
- cooperate in the formation of a write chain linking each of the data processing entities that issued a write to the given memory block, and
- ensure that a prior data processing entity in the write chain completed its write before completing the respective data processing entity's write.
5 more elements
Dependencies are inferred from the claim text.