System featuring memory modules that include an integrated circuit buffer devices

A system comprising:

• a controller device;
• a first point-to-point link coupled to the controller device and a first connector;
• a second point-to-point link coupled to the controller device and a second connector;
• a first memory module including:
• a first plurality of integrated circuit memory devices;
• and
• a first integrated circuit buffer device coupled to the first plurality of integrated circuit memory devices, wherein, when the first memory module is mated to the first connector, the controller device communicates with the first plurality of integrated circuit memory devices over the first point-to-point link using the first integrated circuit buffer device;
• and
• a second memory module including:
• a second plurality of integrated circuit memory devices;
• and
• a second integrated circuit buffer device coupled to the second plurality of integrated circuit memory devices, wherein, when the second memory module is mated to the second connector, the controller device communicates with the second plurality of integrated circuit memory devices over the second point-to-point link using the second integrated circuit buffer device.

A system comprising:

• a printed circuit board;
• a controller device disposed on the printed circuit board;
• a first point-to-point link coupled to the controller device;
• and
• a first socket disposed on the printed circuit board, the first socket to receive a first memory module, wherein the first memory module includes:
• a plurality of integrated circuit memory devices;
• and
• an integrated circuit buffer device coupled to the plurality of integrated circuit memory devices, wherein, when the first socket receives the first memory module:
• the integrated circuit buffer device is operable to receive write data, control information and address information from the controller device over the first point-to-point link;
• the integrated circuit buffer device is operable to transmit control signals corresponding to the control information to the plurality of integrated circuit memory devices;
• the integrated circuit buffer device is operable to receive read data from the plurality of integrated circuit memory devices in response to the control information, wherein the control information specifies a read command;
• and
• the integrated circuit buffer device is operable to transmit the read data to the controller device over the first point-to-point link.

A system comprising:

• a printed circuit board;
• a controller device disposed on the printed circuit board;
• a first point-to-point link coupled to the controller device;
• a first socket disposed on the printed circuit board, the first socket to receive a first memory module, wherein the first memory module includes:
• a plurality of integrated circuit memory devices;
• an integrated circuit buffer device coupled to the plurality of integrated circuit memory devices, wherein, when the first socket receives the first memory module:
• the first integrated circuit buffer device is operable to receive write data, control information and address information from the controller device over the first point-to-point link;
• the first integrated circuit buffer device is operable to transmit control signals corresponding to the control information to the plurality of integrated circuit memory devices;
• the first integrated circuit buffer device is operable to receive read data from the plurality of integrated circuit memory devices in response to the control information, wherein the control information specifies a read command;
• and
• the first integrated circuit buffer device is operable to transmit the read data to the controller device over the first point-to-point link;
• and
• a second socket disposed on the printed circuit board, the second socket to receive a second memory module;
• and
• a second point-to-point link coupled to the second socket and the controller device, wherein the controller device is operable to communicate with the second memory module using the second point-to-point link when the second socket receives the second memory module.