Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port

A hybrid computer system comprising:

• at least one microprocessor;
• a memory block:
• a memory controller coupled to said microprocessor and said memory block for controlling accesses to said memory block by said at least one microprocessor, said memory controller further coupled to an adaptive processor port and a computer system clustering hub;
• and
• at least one adaptive processor coupled to said adaptive processor port, said memory controller further controlling access to said memory block by said at least one adaptive processor, wherein said at least one microprocessor and said adaptive processor exhibit equal memory bandwidth and latency.

A computer system comprising:

• first and second processing elements wherein said second processing element comprises an adaptive processor;
• a memory block;
• and
• a memory controller coupled to said first processing element through a first bus and said second processing element through a second bus, said memory controller further coupled to a computer system clustering hub, said memory controller for controlling accesses to said memory block by said first and second processing elements,
• wherein said first and second processing elements exhibit equal memory bandwidth and latency.