High performance carry chain with reduced macrocell logic and fast carry lookahead
AssigneeCypress Semiconductor Corporation
InventorsHaneef D. Mohammed, Rochan Sankar
Life of this patent
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Abstract
A method for computing a sum or difference and a carry-out of numbers in product-term based programmable logic comprising the steps of: (A) generating (i) a portion of the sum or difference and (ii) a lookahead carry output in each of a plurality of logic blocks; (B) communicating the lookahead carry output of each of the logic blocks to a carry input of a next logic block; (C) presenting the lookahead carry output of a last logic block as the carry-out.
Claims20
A method for computing a sum or difference and a carry-out of numbers in product-term based programmable logic comprising the steps of:
- (A) configuring a plurality of macrocells as a ripple carry chain in each of a plurality of logic blocks of a product-term based programmable logic device, wherein an output of a carry generator multiplexer of a first macrocell of said ripple carry chain in each of said plurality of logic blocks is presented as a carry input to a lookahead carry generator in each of said plurality of logic blocks;
- (B) generating (i) a portion of said sum or difference and (ii) a lookahead carry output in each of said plurality of logic blocks;
- (C) communicating said lookahead carry output of each of said logic blocks to a carry input of a next logic block;
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- (D) presenting said lookahead carry output of a last logic block as said carry-out.
A method for computing a sum or difference and a carry-out of numbers in product-term based programmable logic comprising the steps of:
- (A) configuring a plurality of first logic blocks to each generate (i) a number of sum or difference bits, (ii) a block carry-propagate signal, (iii) a block carry-generate signal, and (iv) a block carry output signal in response to (i) a plurality of inverted carry-propagate product terms, (ii) a plurality of carry-generate product terms, and (iii) either a first carry input signal, a second carry input signal, or one of said block carry output signals, wherein (i) each of said plurality of first logic blocks comprises (a) a plurality of macrocells configured as a ripple carry chain and (b) a lookahead carry generator and (ii) an output of a carry Generator multiplexer of a first macrocell of said ripple carry chain in each of said plurality of logic blocks is connected to a carry input of said lookahead carry generator in each of said plurality of logic blocks;
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- (B) configuring one or more second logic blocks to generate a plurality of said second carry input signals in response to (i) a plurality of block carry-propagate signals (ii) a plurality of block carry-generate signals and (iii) said first carry input signal.
Dependencies are inferred from the claim text.