Floating point multiplier for delimited operands

A system for providing a floating point product comprising:

• a multiplying circuit for multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages, wherein an error introduced by the subprecise operand is corrected by performing an operation in conjunction with a one of the plurality of intermediate stages utilizing a compensating summand;
• and
• a creating circuit for creating the compensating summand comprising:
• a determining circuit for determining the position of a delimiter bit contained within a first significand corresponding to the subprecise operand;
• and
• a generating circuit for generating the compensating summand utilizing the determined position of the delimiter bit, wherein the compensating summand is initially equal to a second significand corresponding to the non-subprecise operand.

A computer-readable medium on which is stored a set of instructions for providing a floating point product, which when executed perform stages comprising:

• multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages;
• and
• correcting an error introduced by the subprecise operand by:
• performing an operation in conjunction with a one of the plurality of intermediate stages utilizing a compensating summand;
• determining the position of a delimiter bit contained within a first significand corresponding to the subprecise operand;
• and
• calculating the compensating summand utilizing the determined position of the delimiter bit, wherein the compensating summand is initially equal to a second significand corresponding to the non-subprecise operand.