Master-slave communication system and electronic apparatus utilizing such system
AssigneeRohm Co., Ltd.
InventorsWataru Suzuki, Hiroshi Miura
Life of this patent
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AssigneeRohm Co., Ltd.
InventorsWataru Suzuki, Hiroshi Miura
Estimating the term…
A communication system has a master device and a slave device clocked by the system clock generated by the master device for data transfer between them. When no data transfer takes place between them for a predetermined period, the slave device goes into a sleep mode. The slave device in the sleep mode can return to the active mode when it receives a system clock. Thus, the slave device can be placed in the sleep mode and return to the active mode without any additional signal lines. The communication system can save a large amount of power during the sleep.
A communication system, comprising:
A communication system, comprising:
A communication system, comprising:
A communication system, comprising:
An electronic apparatus having a communication system including:
An electronic apparatus having a communication system including:
An electronic apparatus having a communication system which includes a master device generating a system clock and at least one slave device connected with said master device by a clock line and at least one data line, wherein
An electronic apparatus having a communication system which includes a master device generating a system clock and at least one slave device connected with said master device by a clock line and at least one data line, wherein
Dependencies are inferred from the claim text.
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Using universal interface adapter: for adaptation of a particular data processing system to different peripheral devices
On a serial bus, e.g. I2C bus, SPI bus: using a clocked protocol
Energy efficient computing
Computing and data processing
Term ended 30 Jun 2023 (estimated)
The invention relates to a master-slave communication system for use in serial data transfer between a master device and a slave device, and to electronic apparatus utilizing such a system.
In conventional master-slave systems transferring data, a limited number of data transfer lines including a clock line, data lines, and chip selection lines are established between them to transfer synchronized serial data. Such conventional master-slave communication systems are widely used for inter-chip communication in many electronic apparatuses including cellular phones.
In this type of conventional communication system, slave devices must be held active at all time in order to wait for incoming signals. Therefore, the slave devices cannot be inactivated (sleep mode) even when they do not receive any data for a long time.
The invention will now be described by way of example with reference to the accompanying drawings, in which:
FIG. 1 is a block diagram of a first communication system according to the invention;
FIG. 2 is a timing diagram of the slave device shown in FIG. 1 returning from a sleep mode to an active mode;
Referring now to FIG. 1, there is shown a first embodiment of a master-slave communication system according to the invention. FIG. 2 shows a timing diagram of the communication system of FIG. 1, with the slave device in a sleep mode returning to an active mode. Flowcharts of FIGS. 3(a) and (b) depict the operations of the communication system carried out by the master device (FIG. 3(a)) and the slave device (FIG. 3(b)).
As shown in FIG. 1, a first communication system 100 has a slave device 10 and a master device 50, which are connected by a system clock line S1, an up data line S2, and a down data line S3. A chip select signal line (not shown) may be also connected to the chip as needed.
System clock CLK is generated by the master device 50 and supplied onto the system clock line S1. The master device 50 may be formed of a general purpose one-chip microcomputer. The up data line S2 transmits data TX issued by the slave device 10 to the master device 50. The down data line S3 transmits data RX issued by the master device 50 to the slave device 10. These data are transferred in synchronism with the system clock CLK.