US 7,003,066 B1Granted

Digital phase locked loop with phase selector having minimized number of phase interpolators

AssigneeLattice Semiconductor Corporation

InventorsAntony Davies, Chienkuang Chen, Ling Wang

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Abstract

In one embodiment of the invention, a phase selection unit for generating a recovered clock signal (SCLK), a phase select signal generator generates a phase select signals in response to a FWD signal and a BWD signal from a digital filter. The digital filter asserts the FWD signal if the phase of a SDIN (serial digital input) signal leads the phase of the recovered clock signal, and asserts the BWD signal if the phase of the SDIN (serial digital input) signal lags the phase of the recovered clock signal. A multiplexer receives a number of given clock signals arranged in a predetermined phase order and outputs selected first and second output clock signals, each being one of the given clock signals. A phase interpolator receives the selected first and second output clock signals from the multiplexer to generate the recovered clock signal having a phase that is phase interpolated between the phases of the first and second output clock signals.

Claims18

Dependent claims

A phase selection unit for generating a recovered clock signal, the phase selection unit comprising:

a phase select signal generator for generating a plurality of phase select signals in response to a FWD (forward) signal and a BWD (backward) signal from a digital filter;
wherein said digital filter asserts said FWD signal if the phase of a SDIN (serial digital input) signal leads the phase of said recovered clock signal;
and wherein said digital filter asserts said BWD signal if the phase of said SDIN (serial digital input) signal lags the phase of said recovered clock signal;
a first multiplexer for inputting a predetermined number of given clock signals arranged in a predetermined phase order and for outputting a first output clock signal and a second output clock signal with said first and second output clock signals each being one of said given clock signals;
a first phase interpolator that receives said first and second output clock signals from said multiplexer to generate said recovered clock signal having a phase that is phase interpolated between the phases of said first and second output clock signals;
a multiplexer control circuit that controls said multiplexer to select one of said given clock signals for each of said first and second output clock signals, depending on whether said phase select signals indicates that said FWD signal is asserted or that said BWD signal is asserted such that the phase of said recovered clock signal generated from said phase interpolator increases when said FWD signal is asserted and decreases when said BWD signal is asserted and remains substantially constant when said FWD signal and said BWD signal are not asserted;
a second multiplexer for inputting said predetermined number of given clock signals and for outputting a third output clock signal that has a 180° phase shift from said first output clock signal and for outputting a fourth output clock signal that has a 180° phase shift from said second output clock signal;
and
a second phase interpolator that receives said third and fourth output clock signals to generate a complementary recovered clock signal that has a 180° phase shift from said recovered clock signal and that has a phase that is phase interpolated between the phases of said third and fourth output clock signals.

6 more elements

A phase selection unit for generating a recovered clock signal, the phase selection unit comprising:

means for generating a plurality of phase select signals in response to a FWD (forward) signal and a BWD (backward) signal from a digital filter,
wherein said digital filter asserts said FWD signal if the phase of a SDIN (serial digital input) signal leads the phase of said recovered clock signal;
and wherein said digital filter asserts said BWD signal if the phase of said SDIN (serial digital input) signal lags the phase of said recovered clock signal;
and wherein said phase select signals are arranged in a predetermined order with a selected one of said phase select signals being asserted as a currently asserted phase select signal with the rest of said phase select signals not being asserted;
and wherein a prior one from said currently asserted phase select signal in said order of said phase select signals is asserted as a newly asserted phase select signal when said BWD signal is asserted;
and wherein a subsequent one from said currently asserted phase select signal in said order of said phase select signals is asserted as said newly asserted phase select signal when said FWD signal is asserted;
means for generating said recovered clock signal having a phase that is phase interpolated between a first phase of a first output clock signal and a second phase of a second output clock signal;
and
means for selecting each of said first and second output clock signals as one of a predetermined number of given clock signals arranged in a predetermined phase order, depending on whether said phase select signals indicate that said FWD signal is asserted or that said BWD signal is asserted such that the phase of said recovered clock signal increases when said FWD signal is asserted and decreases when said BWD signal is asserted and remains substantially constant when said FWD signal and said BWD signal are not asserted;
and
means for generating a complementary recovered clock signal that has a 180° phase shift from said recovered clock signal and that has a phase that is phase interpolated between the phases of third and fourth output clock signals, wherein said third output clock signal has a 180° phase shift from said first output clock signal, and wherein said fourth output clock signal has a 180° phase shift from said second output clock signal.

8 more elements

A method for generating a recovered clock signal, comprising:

generating a plurality of phase select signals in response to a FWD (forward) signal and a BWD (backward) signal from a digital filter;
wherein said digital filter asserts said FWD signal if the phase of a SDIN (serial digital input) signal leads the phase of said recovered clock signal;
and wherein said digital filter asserts said BWD signal if the phase of said SDIN (serial digital input) signal lags the phase of said recovered clock signal;
and wherein said phase select signals are arranged in a predetermined order with a selected one of said phase select signals being asserted as a currently asserted phase select signal with the rest of said phase select signals not being asserted;
and wherein a prior one from said currently asserted phase select signal in said order of said phase select signals is asserted as a newly asserted phase select signal when said BWD signal is asserted;
and wherein a subsequent one from said currently asserted phase select signal in said order of said phase select signals is asserted as said newly asserted phase select signal when said FWD signal is asserted;
generating said recovered clock signal having a phase that is phase interpolated between a first phase of a first output clock signal and a second phase of a second output clock signal;
selecting each of said first and second output clock signals as one of a predetermined number of given clock signals arranged in a predetermined phase order, depending on whether said phase select signals indicate that said FWD signal is asserted or that said BWD signal is asserted such that the phase of said recovered clock signal increases when said FWD signal is asserted and decreases when said BWD signal is asserted and remains substantially constant when said FWD signal and said BWD signal are not asserted;
and
generating a complementary recovered clock signal that has a 180° phase shift from said recovered clock signal and that has a phase that is phase interpolated between the phases of third and fourth output clock signals, wherein said third output clock signal has a 180° phase shift from said first output clock signal, and wherein said fourth output clock signal has a 180° phase shift from said second output clock signal.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/006,559Filed 3 Dec 2001
Granted: 21 Feb 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03L 7/0814
And where no voltage or current controlled oscillator is used: the phase shifting device being digitally controlled
H03L 7/095
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using a lock detector
H04L 7/0337
Using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop:…
H03L
Automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or