US 7,003,065 B2 · PLL cycle slip detection

Abstract

A cycle slip detector interfaces with a phase/frequency detector (PFD), such as might be used in a phase-locked loop circuit (PLL), and indicates when cycle slips occur in the PFD. Typically, the PFD generates output control signals as a function of the phase difference between first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD provides linear phase comparison between its input signals, provided their relative phase difference does not exceed ±2π radians. If one of the two signals leads or lags the other by more than that amount, a cycle slip occurs, and the PFD responds nonlinearly. The cycle slip detector provides logic for detecting and indicating leading and lagging cycle slips as they occur in the PDF, and is typically implemented as a minimal arrangement of logic gates and flip-flops.

Claims23

Dependent claims

A circuit for use in a phase-looked loop (PLL) comprising:

a phase detector comprising:
first and second input circuits to generate first and second PLL control signals responsive to clock edges in first and second input signals, respectively;
and
a reset circuit to generate a reset signal based on said first and second PLL control signals to reset said first and second input circuits;
and
a cycle slip detector for each one of said first and second input circuits, each said cycle slip detector generating a slip indication signal based on said reset signal, a corresponding one of said first and second input signals, and a corresponding one of said first and second PLL control signals;
and
wherein each said cycle slip detector comprises slip detection logic to generate said slip indication signal when a clock edge in said corresponding one of said first and second input signals is received during said reset signal.

5 more elements

A phase-locked loop (PLL) comprising:

a phase detector to generate first and second PLL control signals based on a detected phase difference between respective clock edges in first and second input signals, said phase detector comprising:
first and second input circuits to generate first and second PLL control signals responsive to clock edges in first and second input signals, respectively;
and
a reset circuit to generate a reset signal based on said first and second PLL control signals to reset said first and second input circuits;
and
a control circuit to generate a control signal based on said first and second PLL control signals;
a controllable oscillator to generate an output signal at a frequency based on said control signal;
and
a first cycle slip detector to generate a first cycle slip indicator signal when a clock edge in said first input signal occurs during said reset signal;
and
a second cycle slip detector to generate a second cycle slip indicator when a clock edge in said second input signal occurs during said reset signal;
wherein said first input signal is derived from a reference clock signal and said second input signal is derived from a frequency-controlled output of said PLL.

9 more elements

A radio transceiver comprising:

a receiver to receive a remotely transmitted signal at a receive frequency;
a transmitter to generate a transmit signal at a carrier frequency;
and
a frequency synthesizer to generate a first output signal bearing on said receive frequency and a second output signal bearing on said carrier frequency, said frequency synthesizer comprising:
a reference clock circuit to generate a reference clock signal;
and
first and second phase-locked loops (PLLs) to generate said first and second output signals, respectively, at least one of said first and second PLLs comprising:
a phase detector to generate first and second PLL control signals based on a detected phase difference between respective clock edges in first and second input signals, said first input signal derived from said reference clock signal and said second input signal derived from a corresponding one of said first and second output signals from said frequency synthesizer, said phase detector comprising:
first and second input circuits to generate first and second PLL control signals responsive to said clock edges in said first and second input signals, respectively;
and
a reset circuit to generate a reset signal based on said first and second PLL control signals to reset said first and second input circuits;
and
a control circuit to generate a control signal based on said first and second PLL control signals;
a controllable oscillator to generate said corresponding one of said first and second output signals at a frequency based on said control signal;
and
a first cycle slip detector to generate a first cycle sup indicator signal when a clock edge in said first input signal occurs during said reset signal;
and
a second cycle slip detector to generate a second cycle slip indicator when a clock edge in said second input signal occurs during said reset signal.

15 more elements

A method of detecting cycle slip in a phase detector circuit, the method comprising:

operating said phase detector to generate first and second PLL control signals based on latching respective first clock edges in first and second input signals;
resetting said phase detector with a reset pulse after both said first clock edges occur to make said phase detector responsive to next clock edges in said first and second input signals;
generating a slip indicator signal in response to at least one of said next clock edges occurring before said reset pulse, and in response to any clock edge in at least one of said first and second input signals occurring during said reset pulse.

Dependencies are inferred from the claim text.

PLL cycle slip detection

Life of this patent

PLL cycle slip detection

Life of this patent

Abstract

Claims23