US 7,003,024 B2Granted

Semiconductor device

AssigneeHitachi, Ltd.

InventorsEiji Kubo, Tetsuya Nakagawa, Kosaku Aida, Nobuya Kasai, Mark Walton

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Abstract

A semiconductor device comprises a DSP (Digital Signal Processor), a CPU for controlling the DSP and an interface circuit. The interface circuit comprises an input circuit, a gain-adjusting circuit and an output circuit. The input circuit inputs a digital signal and supplies the signal to the DSP synchronously with a first clock signal. The gain-adjusting circuit is capable of adjusting the gain of the digital signal supplied to the input circuit. The output circuit adds a digital signal received from the DSP to the digital signal with the gain thereof adjusted and outputs a signal obtained as a result of the addition synchronously with the first clock signal. A signal path extended from the input circuit through the gain-adjusting circuit to the output circuit forms hardware. A digital signal to be transmitted propagates through the hardware to be subjected to the so-called side-tone processing. As a result, it is possible to provide a semiconductor device capable of generating a side tone without increasing the magnitude of a load borne by a CPU and without requiring an external circuit component.

Claims7

Dependent claims

A semiconductor device formed on a single semiconductor chip, comprising:

a digital-signal-processing circuit;
a CPU controlling said digital-signal-processing circuit:
and
an interface circuit inputting a digital signal synchronously with a first clock signal and supplying said input digital signal to said digital-signal-processing circuit and outputting digital data processed by said digital-signal-processing circuit synchronously with said first clock signal,
wherein said interface circuit includes:
an input circuit inputting said digital signal synchronously with said first clock signal and supplying said input digital signal to said digital-signal-processing circuit;
a gain-adjusting circuit adjusting a gain of said digital signal supplied to said input circuit;
and
an output circuit adding said digital signal with said gain thereof adjusted to a digital signal supplied from said digital-signal-processing circuit and outputting a resulting digital signal synchronously with said first clock signal;
wherein said input circuit comprises:
an input shift register inputting and shifting the digital signal synchronously with said first clock signal;
and
an input register latching the digital signal shifted in said input shift register synchronously with a second clock signal.

10 more elements

Dependencies are inferred from the claim text.