Semiconductor memory
AssigneeFujitsu Limited
InventorHitoshi Ikeda
Life of this patent
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Abstract
A latch signal generator generates a latch signal in synchronization with later one of a timing at which a delayed chip enable signal obtained by delaying a chip enable signal is activated and a transition timing of a clock signal. A latch circuit latches an input signal received by a signal input buffer, in synchronization with the latch signal. By changing the timing the latch signal is generated in accordance with set-up time of the input signal with respect to the clock signal, it is possible to reduce the stand-by current and prevent malfunction of a semiconductor memory caused by improper latch of the input signal.
Claims4
A semiconductor memory comprising:
- a memory core having a memory cell;
- a clock input buffer receiving a clock signal to operate an internal circuit;
- an enable input buffer receiving a chip enable signal which enables said memory core to operate;
- a signal input buffer which is activated to receive an input signal while said chip enable signal is active, and which is deactivated while said chip enable signal is not active;
- a latch signal generator generating a latch signal in synchronization with later one of a timing at which a delayed chip enable signal obtained by delaying said chip enable signal is activated and a transition timing of said clock signal received by said clock input buffer;
- and
- a latch circuit latching the input signal received by said signal input buffer in synchronization with said latch signal.
Dependencies are inferred from the claim text.