Dual word line mode for DRAMs
AssigneesUnited Memories, Inc., Sony Corporation
InventorsMichael C. Parris, Douglas Blaine Butler, Oscar Frederick Jones, Jr.
Life of this patent
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Abstract
An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a second operational mode where two or more memory cells are dedicated to each data bit, and providing a word line sequence when first converting stored data in the array of memory cells from the first operational mode to the second operational mode. The word line sequence includes activating a first word line, developing a valid signal on a corresponding bit line, and then activating a second word line while the first word line is still active.
Claims20
An integrated circuit memory comprising:
- a plurality of bit lines;
- a plurality of word lines;
- a plurality of memory cells each coupled to one of the plurality of bit lines and to one of the plurality of word lines;
- row decoder circuitry for individually activating the word lines in a first operational mode and for simultaneously activating at least two word lines in a second operational mode;
- and
- means for providing a word line sequence when first converting stored data in the plurality of memory cells from the first operational mode to the second operational mode.
A method of operating an integrated circuit memory including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each coupled to one of the plurality of bit lines and to one of the plurality of word lines, the method comprising:
- individually activating the word lines in a first operational mode;
- simultaneously activating at least two word lines in a second operational mode;
- and
- providing a word line sequence when first converting stored data in the plurality of memory cells from the first operational mode to the second operational mode.
A predecoder for an integrated circuit memory for switching between a first operational mode and a second operational mode comprising:
- an input section having first and second address inputs;
- and
- an output section coupled to the input section having a control signal input and an output for providing an output signal,
- wherein the output signal is responsive to the data states of the first and second address inputs in the first operational mode, and the output signal is forced to a data state in response to control signal on the control signal input in the second operational mode.
Dependencies are inferred from the claim text.