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US 7,002,872 B2Granted
Semiconductor memory device with a decoupling capacitor
AssigneeSamsung Electronics Co., Ltd.
InventorsHyong-ryol Hwang, Young-hun Seo, Jae-yoon Sim
Life of this patent
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Abstract
A semiconductor memory device includes a core block having sub-arrays and sense amplifier regions. First and second charge storing regions are disposed at sides of the core block. First and second decoupling capacitors are formed at the first and second charge storing regions, respectively. A plurality of first voltage supply lines are disposed to supply a power supply voltage to the sense amplifier regions and are connected to one electrode of each of the first and second decoupling capacitors. A plurality of second voltage supply lines are disposed to supply a ground voltage to the sense amplifier regions and are connected to the other electrode of each of the first and second decoupling capacitors.
Claims42
A semiconductor memory device, comprising:
- a core block including a plurality of sub-arrays and a plurality of sense amplifier regions;
- a plurality of first voltage supply lines capable of supplying a first operating voltage to the plurality of sense amplifier regions;
- a plurality of second voltage supply lines capable of supplying a second operating voltage to the sense amplifier regions;
- and
- a first charge storing region arranged at one side of the core block and including first charge storing means connected to the first and second voltage supply lines;
- and
- a second charge storing region distinct from the first storing region arranged at an opposite side of the one side and including second charge storing means connected to the first and second voltage supply lines.
4 more elements
A semiconductor memory device comprising:
- a core block including a plurality of sub-arrays arranged in rows and columns and a plurality of sense amplifier regions each arranged between sub-arrays;
- a plurality of first voltage supply lines capable of supplying a first operating voltage to the sense amplifier regions;
- a plurality of second voltage supply lines capable of supplying a second operating voltage to the sense amplifier regions;
- and
- a first charge storing region disposed at one side of the core block, the first charge storing region capable of connecting to the first supply lines;
- a second charge storing region disposed at another side of the core block different than the one side, the second charge storing region capable of connecting to the second supply lines.
3 more elements
A semiconductor memory device, comprising:
- a core block including a plurality of sub-arrays arranged in rows and columns, a plurality of word line driving regions disposed between sub-arrays adjacent in a row direction, a plurality of sense amplifier regions each arranged between sub-arrays adjacent in a column direction, and a plurality of conjunction regions disposed between sense amplifier regions adjacent in the row direction;
- a plurality of first voltage supply lines disposed on sense amplifier and conjunction regions, capable of supplying a first operating voltage to the sense amplifier regions;
- a plurality of second voltage supply lines disposed on sense amplifier and conjunction regions, capable of supplying a second operating voltage to the sense amplifier regions;
- and
- first and second charge storing regions respectively disposed at opposing sides of the core block;
- where the first and second charge storing regions comprise first and second charge storing regions capable of connecting to first and second voltage supply lines, respectively.
3 more elements
A memory device, comprising:
- a core block including a plurality of sub-arrays arranged in rows and columns, a plurality of word line driving regions disposed between sub-arrays adjacent in a row direction, a plurality of sense amplifier regions each arranged between sub-arrays adjacent in a column direction, and a plurality of conjunction regions disposed between sense amplifier regions adjacent in the row direction;
- a plurality of first voltage supply lines disposed on sense amplifier and conjunction regions, capable of supplying a first operating voltage to the sense amplifier regions;
- a plurality of second voltage supply lines disposed on sense amplifier and conjunction regions, capable of supplying a second operating voltage to the sense amplifier regions;
- first and second charge storing regions disposed at sides of the core block;
- a column selector block disposed adjacent to the other sides of the core block;
- a plurality of third voltage supply lines disposed on sense amplifier and word line driving regions, capable of supplying the first operating voltage to sense amplifiers;
- a plurality of fourth voltage supply lines disposed on sense amplifier and word line driving regions, capable of supplying the second operating voltage to the sense amplifiers;
- and
- third and fourth charge storing means connected to the third and fourth voltage supply lines, respectively;
- where the first and third voltage supply lines are intersected and interconnected at the conjunction regions;
- where the second and fourth voltage supply lines are intersected and interconnected at the conjunction regions;
- where the first and second charge storing regions comprise first and second charge storing regions capable of connecting to first and second voltage supply lines, respectively;
- and
- where the third and fourth charge storing means are disposed at other sides of the core block.
11 more elements
A memory device, comprising:
- a core block including a plurality of sub-arrays arranged in rows and columns, a plurality of word line driving regions disposed between sub-arrays adjacent in a row direction, a plurality of sense amplifier regions each arranged between sub-arrays adjacent in a column direction, and a plurality of conjunction regions disposed between sense amplifier regions adjacent in the row direction;
- a plurality of first voltage supply lines disposed on sense amplifier and conjunction regions, capable of supplying a first operating voltage to the sense amplifier regions;
- a plurality of second voltage supply lines disposed on sense amplifier and conjunction regions, capable of supplying a second operating voltage to the sense amplifier regions;
- first and second charge storing regions disposed at sides of the core block;
- a plurality of third voltage supply lines disposed on sense amplifier and word line driving regions, capable of supplying the first operating voltage to sense amplifiers;
- a plurality of fourth voltage supply lines disposed on sense amplifier and word line driving regions, capable of supplying the second operating voltage to the sense amplifiers;
- and
- third and fourth charge storing means connected to third and fourth voltage supply lines, respectively;
- where the first and third voltage supply lines are intersected and interconnected at the conjunction regions;
- where the second and fourth voltage supply lines are intersected and interconnected at the conjunction regions;
- where the first and second charge storing regions comprise first and second charge storing regions capable of connecting to first and second voltage supply lines, respectively;
- where the third and fourth charge storing means are disposed at other sides of the core block;
- and
- where the third charge storing means comprises:
- a third decoupling capacitor including a third active region formed at a third side of the core block;
- a plurality of fifth conductive films formed over the third active region and capable of connecting to the third voltage supply lines;
- and
- a sixth conductive film formed over the third active region and connected to the fourth voltage supply lines;
- where the sixth conductive film is capable of electrically connecting to the third active region through a third plurality of contacts.
16 more elements
A semiconductor memory device, comprising:
- a core block including a plurality of sub-arrays arranged in rows and columns, a plurality of word line driving regions disposed between sub-arrays adjacent in a row direction, a plurality of sense amplifier regions each arranged between sub-arrays adjacent in a column direction, and a plurality of conjunction regions disposed between sense amplifier regions adjacent in the row direction;
- a plurality of first voltage supply lines disposed on sense amplifier and conjunction regions, capable of supplying a first operating voltage to the sense amplifier regions;
- a plurality of second voltage supply lines disposed on sense amplifier and conjunction regions, capable of supplying a second operating voltage to the sense amplifier regions;
- and
- first and second charge storing regions disposed at sides of the core block;
- where the first and second charge storing regions comprise first and second charge storing regions capable of connecting to first and second voltage supply lines, respectively;
- where the first operating voltage is a supply voltage and the second operating voltage is a ground voltage.
4 more elements
A semiconductor memory device, comprising:
- a core block including a plurality of sub-arrays, a plurality of word line driving regions disposed between sub-arrays, a plurality of sense amplifier regions each arranged between sub-arrays, each sense amplifier regions having a plurality of sense amplifiers, and a plurality of conjunction regions each disposed between sense amplifier regions;
- a plurality of first voltage supply lines disposed on sense amplifier and conjunction regions, capable of supplying a first operating voltage to the sense amplifier regions;
- a plurality of second voltage supply lines disposed on sense amplifier and conjunction regions, capable of supplying a second operating voltage to the sense amplifier regions;
- a plurality of third voltage supply lines disposed on sense amplifier and conjunction regions, capable of supplying the first operating voltage to sense amplifier regions;
- a plurality of fourth voltage supply lines disposed on sense amplifier and conjunction regions, capable of supplying the second operating voltage to the sense amplifier regions;
- and
- a charge storing region arranged to surround the core region and comprising charge storing means connected to the first, second, third, and fourth voltage supply lines.
4 more elements
A semiconductor memory device, comprising:
- a core block including a plurality of sub-arrays arranged in rows and columns and a plurality of sense amplifier regions each arranged between sub-arrays adjacent in a column direction;
- first and second charge storing regions disposed at a first and second sides, respectively, of the core block, first and second decoupling capacitors being formed at the first and second charge storing regions, respectively;
- a plurality of first voltage supply lines connected to first electrodes of the first and second decoupling capacitors, the plurality of first voltage supply lines being capable of supplying a first operating voltage to the sense amplifier regions;
- and
- a plurality of second voltage supply lines connected to second electrodes of the first and second decoupling capacitors, the plurality of second voltage supply lines being capable of supplying a second operating voltage to the sense amplifier regions.
2 more elements
A semiconductor memory device comprising:
- a core block including a plurality of sub-arrays arranged in rows and columns, a plurality of word line driving regions disposed between adjacent sub-arrays, a plurality of sense amplifier regions each arranged between adjacent sub-arrays, and a plurality of conjunction regions each disposed between the sense amplifier regions;
- a plurality of first voltage supply lines disposed on sense amplifier and conjunction regions;
- a plurality of second voltage supply lines disposed on the sense amplifier and conjunction regions;
- a plurality of third voltage supply lines disposed on sense amplifier and word line driving regions;
- a plurality of fourth voltage supply lines disposed on the sense amplifier and word line driving regions;
- and
- a charge storing region disposed to surround the core block and having a decoupling capacitor capable of storing a charge;
- where the first and third voltage supply lines are connected to the one electrode and the second and fourth voltage supply lines are connected to the another electrode.
5 more elements
A semiconductor memory device, comprising:
- a core block including a plurality of sub-arrays arranged in rows and columns, a plurality of word line driving regions disposed between adjacent sub-arrays adjacent, a plurality of sense amplifier regions each arranged between adjacent sub-arrays, and a plurality of conjunction regions each disposed between adjacent sense amplifier regions;
- a plurality of first voltage supply lines disposed on sense amplifier and conjunction regions;
- a plurality of second voltage supply lines disposed on the sense amplifier and conjunction regions;
- a plurality of third voltage supply lines disposed on sense amplifier and word line driving regions;
- a plurality of fourth voltage supply lines disposed on the sense amplifier and word line driving regions;
- and
- first and second charge storing regions disposed respectively at two sides of the core block and including first and second decoupling capacitors, respectively;
- where the third voltage supply lines are connected to first electrodes of the first and second decoupling capacitors and the fourth voltage supply lines are connected to second electrodes of the first and second decoupling capacitor.
5 more elements
Dependencies are inferred from the claim text.