Asynchronous pseudo SRAM and access method therefor

A semiconductor integrated circuit device comprising:

• a memory cell array;
• a row address buffer which receives a row address signal that indicates a row address of the memory cell array;
• a column address buffer which receives a column address signal that indicates a column address of the memory cell array;
• a CE buffer which receives an external chip enable signal;
• a WE buffer which receives an external write enable signal;
• a first row address latch which latches the row address signal output from the row address buffer;
• a second row address latch which latches the row address signal output from the first row address latch and outputs an internal row address signal;
• a first column address latch which latches the column address signal output from the column address buffer;
• a second column address latch which latches the column address signal output from the first column address latch and outputs an internal column address signal;
• a row address transition detection circuit which detects transition of the row address signal output from the first row address latch;
• a column address transition detection circuit which detects transition of the column address signal output from the first column address latch;
• a chip enable transition detection circuit which detects transition of the external chip enable signal output from the CE buffer;
• a write enable transition detection circuit which detects transition of the external write enable signal output from the WE buffer;
• an ATD AND circuit which ANDs detection results from the row address transition detection circuit, the column address transition detection circuit, the chip enable transition detection circuit, and the write enable transition detection circuit;
• and
• an internal CE control circuit which comprises a timeout circuit that controls a cycle operation of the memory cell array, controls a row system circuit and a column system circuit to access the memory cell array and also controls the row address buffer, the column address buffer, the first and second row address latches, and the first and second column address latches on the basis of an AND signal output from the ATD AND circuit, causes the first and second row address latches and the first and second column address latches to respectively latch a row address and a column address at operation start time, which are output from the row address buffer and the column address buffer, during the operation of the memory cell array, and when the row address transition detection circuit detects the transition of the row address or the column address transition detection circuit detects the transition of the column address during the cycle operation, causes the second row address latch and the second column address latch to respectively latch, after an end of the operation of the memory cell array, a row address and a column address that are currently latched by the first row address latch and the first column address latch so as to control access to the memory cell array.

An access method for a semiconductor integrated circuit device including a memory cell array, an address buffer which receives an address signal that indicates an address of the memory cell array, a latch circuit which latches the address output from the address buffer, an address transition detection circuit which detects transition of the address, and a control circuit which comprises a timeout circuit that controls a cycle operation of the memory cell array on the basis of a detection result from the address transition detection circuit, comprising:

• causing the latch circuit to latch an address at operation start time during the operation of the memory cell array;
• causing the address transition detection circuit to detect the transition of the address during the cycle operation;
• when the transition of the address is detected, causing the latch circuit to latch, after an end of the operation of the memory cell array, an address that is currently input to the address buffer;
• and
• executing the next cycle operation of the memory cell array in accordance with the address latched by the latch circuit.

An access method for a semiconductor integrated circuit device including a memory cell array, a row address buffer which receives a row address signal that indicates a row address of the memory cell array, a column address buffer which receives a column address signal that indicates a column address of the memory cell array, a CE buffer which receives an external chip enable signal, a WE buffer which receives an external write enable signal, a first row address latch which latches the row address signal output from the row address buffer, a second row address latch which latches the row address signal output from the first row address latch and outputs an internal row address signal, a first column address latch which latches the column address signal output from the column address buffer, a second column address latch which latches the column address signal output from the first column address latch and outputs an internal column address signal, a row address transition detection circuit which detects transition of the row address signal output from the first row address latch, a column address transition detection circuit which detects transition of the column address signal output from the first column address latch, a chip enable transition detection circuit which detects transition of the external chip enable signal output from the CE buffer, a write enable transition detection circuit which detects transition of the external write enable signal output from the WE buffer, an ATD AND circuit which ANDs detection results from the row address transition detection circuit, the column address transition detection circuit, the chip enable transition detection circuit, and the write enable transition detection circuit, and an internal CE control circuit which comprises a timeout circuit that controls a cycle operation of the memory cell array, controls a row system circuit and a column system circuit to access the memory cell array, and also controls the row address buffer, the column address buffer, the first and second row address latches, and the first and second column address latches on the basis of an AND signal output from the ATD AND circuit, comprising:

• causing the first and second row address latches and the first and second column address latches to respectively latch a row address and a column address at operation start time, which are output from the row address buffer and the column address buffer, during the operation of the memory cell array;
• causing the row address transition detection circuit to detect the transition of the row address or causing the column address transition detection circuit to detect the transition of the column address during the cycle operation;
• when the transition of the row address or column address is detected, causing the second row address latch and the second column address latch to respectively latch, after an end of the operation of the memory cell array, a row address and a column address that are currently latched by the first row address latch and the first column address latch;
• and
• executing the next cycle operation of the memory cell array in accordance with the addresses latched by the second row address latch and the second column address latch.