Speeding up the power-up procedure for low power RAM
AssigneeEtron Technology, Inc.
InventorJen-Shou Hsu
Life of this patent
Estimating the term…
Abstract
An internal power system for a low power memory chip is described that provides a large capacity internal power source during chip power up and during an active state whereby memory operations are carried out. A memory chip standby state allows reduced chip power where the large capacity power source is turned off, and the memory chip internal voltages are provided by a small capacity power source. Switching between the standby and active states of the low power memory chip is accomplished by turning on and off a standby signal. The internal and external chip voltages are monitored during chip power up to insure that predetermined voltage levels have been reached before turning off the large capacity power source and placing the chip into a standby state.
Claims25
An internal power system for a memory chip, comprising:
- a) a low power memory chip,
- b) a small capacity voltage converter,
- c) a large capacity voltage converter,
- d) a first and a second control signal,
- e) said first and second control signals control said large capacity voltage converter during power on and operation of said memory chip to provide charging capacity during bring up and memory operations of said memory chip and to conserve power during a standby state of said memory chip.
A method of power control for of a low power memory chip, comprising:
- a) turning on an external power of a low power memory chip,
- b) turning on a first control signal coupled to a power circuitry internal to said memory chip,
- c) turning on a small capacity voltage converter and a large capacity voltage converter which form a power source for said power circuitry,
- d) waiting an amount of time after said external power has stabilized and reached final value, and issuing a second control signal which places said memory chip into a standby state,
- e) turning off said first control signal while said memory chip is in said standby state, which places said memory chip into an active state,
- f) turning on said first control signal while said memory chip is in said active state, which places said memory chip in said standby state.
A power circuit for a low power memory chip, comprising:
- a) a means for controlling a power source internal to a low power memory chip to provide a high capacity to charge internal power circuits during power up of said memory chip,
- b) a means for controlling said power source to conserve power in a standby state,
- c) a means for controlling said power source to provide said high capacity in an active state when memory operations are performed,
- d) a means for switching between said active and said standby states.
Dependencies are inferred from the claim text.