High-speed, two-port dynamic random access memory (DRAM) with a late-write configuration

A semiconductor memory device comprising:

• a cell array having a plurality of memory cells;
• a first X decoder for decoding a row address of an input address externally supplied to said semiconductor memory device;
• a second X decoder for decoding a refresh address;
• a first sense amplifier for normal access;
• a second sense amplifier for refreshing;
• a timer for generating a trigger signal for specifying a refresh cycle;
• and
• a refresh address generation circuit, receiving the trigger signal output from said timer, for generating the refresh address based on the trigger signal;
• wherein
• each of said memory cells includes:
• first and second switch transistors connected in series between a first bit line and a second bit line adjacent to each other;
• and
• a capacitor for data storage connected to a connection node at which the first and second switch transistors are tied;
• the first switch transistor having a control terminal connected to a first word line to be controlled on/off;
• the second switch transistor having a control terminal connected to a second word line adjacent to the first word line to be controlled on/off;
• and wherein
• the first word line is connected to the first X decoder;
• the second word line is connected to the second X decoder;
• said first and second X decoders being disposed to be opposite to each other with said cell array interposed therebetween;
• the first bit line is connected to the first sense amplifier;
• and
• the second bit line is connected to the second sense amplifier;
• said first and second amplifiers being disposed to be opposite to each other with said cell array interposed therebetween;
• said semiconductor memory device further comprising:
• a match detection circuit for comparing the refresh address from said refresh address generation circuit with the row address of the externally supplied write address delayed by a period corresponding to a predetermined number of write cycles to detect whether the refresh address matches the row address or not;
• and
• a control unit for performing control so that
• when a mismatch between the refresh address and the row address of the write address is detected by the match detection circuit, a write operation and a refresh operation are concurrently performed in an identical cycle, in which the write operation is performed by activating the first word line selected as a result of decoding the row address of the write address by said first X decoder, turning on the first switch transistor for the memory cell connected to the first word line, and writing data to said memory cell selected by the write address, while the refresh operation is performed by activating the second word line selected as a result of decoding the refresh address by said second X decoder and using said second sense amplifier on the memory cell connected to the second word line, and
• when the match between the refresh address and the row address of the write address is detected by the match detection circuit, the refresh operation is inhibited, the first word line selected by decoding by said first X decoder is activated, and then the write operation on said memory cell selected by the write address is performed.

A semiconductor memory device which has an interface compatible with that of a static random access memory compliant with a late-write specification, said semiconductor memory device comprising:

• a cell array including a plurality of two-port DRAM cells;
• a refresh address generation circuit;
• a comparator for comparing a refresh address output from the refresh address generation circuit with a write address delayed by a period corresponding to a write access cycle defined in the late-write specification;
• and
• a control unit for performing control so that a refresh operation is stopped when a comparison result by the comparator indicates that the refresh address matches the write address.

A semiconductor memory device comprising:

• a memory cell array including a read/write address input port and a refresh address input port, a read/write access to a memory cell therein specified by an address input from said read/write address input port and a refresh on a memory cell therein specified by an address input from said refresh address input port in synchronization with the read/write access being simultaneously performed;
• an address holding circuit and a data holding circuit for holding the address supplied to an address terminal thereof from an outside of said semiconductor memory device and data supplied to a data terminal thereof from the outside of said semiconductor memory device, respectively;
• a first determination circuit for comparing a row address held in said address holding circuit and the refresh address supplied from said refresh address input port to detect whether the row address matches the refresh address or not;
• a second determination circuit for comparing the address held in said address holding circuit with an externally input read address to detect whether the address held in said address holding circuit matches the externally input read address or not;
• a first control circuit for performing control so that
• when said first determination circuit detects a mismatch, a write operation for writing the data held in said data holding circuit to the memory cell specified by the address, held in said address holding circuit and supplied to said memory cell array from said read/write address input port and a refresh operation on the refresh address are simultaneously performed, in synchronization with the write operation, and
• when said first determination circuit detects the match, the refresh operation is inhibited and the write operation is performed;
• and
• a second control circuit for performing control so that
• when said second determination circuit detects a mismatch, the address held in said address holding circuit is supplied to the memory cell array from said read/write address input port and data is read from the memory cell specified by the address to output from said data terminal;
• and
• when said second determination circuit detects the match, the data is read from said data holding circuit instead of said memory cell array to output from said data terminal.

A method of controlling a semiconductor memory device, said semiconductor memory device comprising:

• a cell array including a plurality of memory cells, each of said memory cells comprising:
• first and second switch transistors connected in series between a bit line for normal access and a bit line for refreshing;
• and
• a capacitor for data storage, connected to a connection node at which the first and second switch transistors are tied;
• a word line for normal access and a word line for refreshing being connected to respective control terminals of the first and second switch transistors;
• said semiconductor memory device having a late-write configuration in which a write to a memory cell selected by a write address supplied to an address terminal of said semiconductor memory device from an outside of said semiconductor memory device is performed, being delayed by at least one write cycle;
• said method comprising the steps of:
• comparing a generated refresh address with the write address externally supplied to the address terminal at least one write cycle earlier to detect whether the refresh address matches the write address or not;
• performing control so that when a mismatch between the refresh address and the row address of the write address is detected, a write operation and a refresh operation are concurrently performed in an identical cycle, in which the write operation is performed by activating the word line for normal access selected by the write address, turning on the first switch transistor for the memory cell connected to said word line for normal access, and writing data to the capacitor through the bit line for normal access, while the refresh operation is performed by activating the word line for refreshing selected by the refresh address, turning on the second switch transistor for the memory cell connected to said word line for refreshing, and reading cell data and restoring said cell data through the bit line for refreshing using a sense amplifier for refreshing connected to said bit line for refreshing;
• and
• when a match between the refresh address and the row address of the write address is detected, the refresh operation is inhibited and the write operation is performed.

A method of controlling a semiconductor memory device comprising a cell array including a plurality of memory cells each requiring a refreshing to hold stored data, an address holding circuit for holding an address input to an address terminal thereof, and a data holding circuit for holding data input to a data terminal thereof, the address and the data supplied from an outside of said semiconductor memory device, said method comprising the steps of:

• storing the externally input address and the data in said address holding circuit and said data holding circuit, respectively;
• comparing a row address of the write address held in said address holding circuit with a refresh address to detect whether the row address matches the refresh address or not, and simultaneously performing a write operation for writing the data held in said data holding circuit to said cell array and a refresh operation on said cell array when a mismatch between the row address of the write address and the refresh address is detected, and inhibiting the refresh operation and performing the write operation when the match between the row address of the write address and the refresh address is detected;
• and
• comparing the write address held in said address holding circuit with an externally input read address to detect whether the write address matches the externally input read address or not, reading data from said cell array for supply from said data terminal when a mismatch is detected, and reading the data held in said data holding circuit for supply from said data terminal when the match is detected.