Refresh control circuit for ICs with a memory array

A memory device comprising:

• a memory cell array having a multitude of memory cells, first and second bitlines, and first and second wordlines, each of said memory cells being coupled to one of said first bitlines, one of said second bitlines, one of said first wordlines, and one of said second wordlines;
• each of said memory cells being accessible through one of said first wordlines and one of said first bitlines by an external port and being accessible through one of said second wordlines and one of said second bitlines by an internal port;
• said external port being connected to input terminals to receive input signals in order to select one of said memory cells for an external data access;
• a refresh control unit generating refresh control signals to control refreshing of the memory cells through said internal port;
• a contention detection circuit, said contention detection circuit receiving a row address in response to an external read or write access through said external port and receiving a refresh address for a row of memory cells to be refreshed, said contention detection circuit suppressing a refresh, if said refresh address equals said row address;
• and
• wherein each one of said memory cells comprises
• a first selection transistor coupled to one of said first wordlines and one of said first bitlines,
• a second selection transistor coupled to one said second wordlines and one of said second bitlines, and
• a storage node connected to said first selection transistor and said second selection transistor.

A memory device comprising:

• a memory cell array having memory cells, each of said memory cells being accessible through a first port and through a second port, only said first port of said first and second ports being accessible by an external address signal to select one of said memory cells;
• and
• a refresh control circuit designed to generate refresh control signals to refresh said memory cells through said second port, wherein said refresh control circuit receives a system clock signal and a reference clock signal, said refresh control circuit has a refresh address counter to provide a sequence of addresses for subsets of memory cells to be refreshed, said memory device having a normal mode and a power-down mode, wherein said refresh address counter is controlled by said system clock signal during the normal mode and is controlled by said reference clock signal during the power-down mode;
• and
• a contention detection circuit receiving an internal or refresh address to access a subset of said memory cells for a refresh operation and an external address to access at least of one said memory cells for a read or write operation, said contention detection circuit suppressing a refresh operation for said subset of said memory cells if the external address accesses a memory cell within the subset of memory cells of the refresh address.

An integrated circuit (IC) comprising:

• a multi-port memory cell array having at least first and second ports;
• a plurality of memory cells accessible by the first and second ports;
• a refresh control unit generating refresh control signals to control refreshing of the memory cells;
• and
• a contention detection circuit to for detecting contention between a refresh operation from one of the ports and a read or write memory access operation from other of the ports and suppressing the refresh operation when contention occurs to allow the read or write memory access to execute.

An IC comprising:

• a plurality of memory cells forming a memory array arranged in rows and columns;
• a refresh control unit generating refresh control signals to control refreshing of the memory cells;
• and
• a contention detection circuit, when a read or write memory access and a refresh operation are to the same row, suppresses the refresh operation to enable execution of the read or write memory access.