US 7,002,863 B2 · Driving a DRAM sense amplifier having low threshold voltage PMOS transistors

Abstract

Circuits and methods for driving a DRAM sense amplifier having low threshold voltage PMOS transistors are described. The source terminal of a low Vtp PMOS transistor is maintained at ground potential during DRAM standby mode. The source terminal of the low Vtp PMOS transistor is raised to an intermediate supply voltage responsive to a transition from DRAM standby mode to either DRAM read mode, write mode, or refresh mode and prior to development of a differential voltage between the gate and drain terminals of the low Vtp PMOS transistor. These circuits and methods advantageously limit current loss through the low Vtp PMOS transistor when the differential voltage develops between the gate and drain terminals of that low Vtp PMOS transistor and in the event of a word line and digital line short-circuit.

Claims22

Dependent claims

An electrical circuit for driving an amplifier operative to amplify a differential voltage between a pair of signal lines to a full digital logic separation, said circuit comprising:

a switch coupled between a voltage source and an input terminal of said amplifier, said switch operative to raise said input terminal to an intermediate voltage between ground potential and a full supply voltage prior to development of said differential voltage between said pair of signal lines;
and
circuitry operative to raise said input terminal of said amplifier to said full supply voltage after said differential voltage develops between said pair of signal lines.

Dependencies are inferred from the claim text.

Driving a DRAM sense amplifier having low threshold voltage PMOS transistors

Life of this patent

Driving a DRAM sense amplifier having low threshold voltage PMOS transistors

Life of this patent

Abstract

Claims22