Multilevel register-file bit-read method and apparatus

A computer system comprising:

• a processor;
• and
• first memory for storing program instructions executable by the processor, wherein the processor includes a register-file bit-read apparatus comprising:
• a first decoder for receiving first address-bit signals and responsively asserting a set of select signals on one of N sets of M select lines;
• N multiplexers, each having Q output nodes and Q pull-ups coupled to the respective Q nodes, and having M selectors, each selector being coupled to a respective one of the N×M select lines and a respective one of N×M register-file cells, wherein the M selectors of such a multiplexer are arranged in Q groups coupled to respective ones of the multiplexer's Q output nodes;
• and
• output logic gates for the respective N multiplexers, such a logic gate having Q inputs coupled to respective ones of the Q output nodes of the gate's multiplexer;
• a second decoder for receiving second address-bit signals and responsively asserting a select signal on an N+1th set of N select lines;
• an N+1th multiplexer having R output nodes and R pull-ups coupled to the respective R nodes, and having N selectors, each coupled to a respective one of the select lines of the second decoder and a respective one of the N output logic gates of the N multiplexers, wherein the N selectors are in R groups coupled to respective ones of the R output nodes;
• and
• an N+1th output logic gate having R inputs, each input being coupled to a respective one of the R output nodes, wherein each multiplexer pull-up is operable to drive its respective multiplexer output node responsive to one of the address-bit signals, wherein such a pull-up includes a transistor having one conducting electrode coupled to a supply voltage having a certain voltage level, another conducting electrode coupled to the pull-up's respective one of the multiplexer output nodes and a gate directly coupled to one of the address-bit signals or a complement of one of the address-bit signals, the address bit signal turning on the transistor if the selected one of the register-file cells is not conductively coupled to the pull-up's node so that the pull-up drives its multiplexer output node toward the voltage level of the supply voltage, and wherein the multiplexer is not directly coupled to any cyclical timing signal.

A method for a register-file bit-read apparatus comprising the steps of:

• receiving first address-bit signals by a first decoder;
• asserting, responsive to the first address-bit signals, a set of select signals on a selected one of N sets of select lines associated with the decoder, wherein each of N multiplexers receives one of the asserted select signals;
• conductively coupling selected register-file cells to first respective output nodes of the N multiplexers responsive to the set of N select signals asserted by the first decoder;
• driving high, for each of the N multiplexers, respective second output nodes responsive to one of the first address-bit signals;
• receiving second address-bit signals by a second decoder;
• receiving, by the N selectors of an N+1th multiplexer associated with the second decoder, respective output signals from the N multiplexers;
• asserting, responsive to the second address-bit signals, a select signal on a selected one of select lines associated with the second decoder;
• conductively coupling a selected one of the output signals from one of the first decoder's N multiplexers to a first output node of the N+1th multiplexer responsive to the select signal asserted by the second decoder;
• and
• driving high, for the N+1th multiplexer, a second output node responsive to one of the second address-bit signals, wherein the driving of such a multiplexer's second output node high responsive to one of the address-bit signals includes the address bit signal or a complement of the address-bit signals, directly turning on a pull-up transistor of such a multiplexer if the selected one of the register-file cells for the multiplexer is not conductively coupled to the second output node, and wherein the N+1 multiplexers are not directly coupled to any cyclical timing signal.