US 7,002,858 B2 · Semiconductor memory device which selectively controls a local input/output line sense amplifier

Abstract

A semiconductor memory device in which a local input/output line sense amplifier may be selectively enabled or disabled. The semiconductor memory device may include a memory cell array block, a redundancy circuit, a switch unit, and/or a control unit. The memory cell array block may include a local input/output line sense amplifier that operates in response to a sense amplifier enable signal. The redundancy circuit may include a redundancy local input/output line sense amplifier that operates in response to the sense amplifier enable signal. The switch unit may selectively output data output from the local input/output line sense amplifier or the redundancy local input/output line sense amplifier, in response to a first select signal and a second select signal. If the redundancy circuit operates, the control unit may generate, in response to the second select signal, a sense amplifier operation control signal that disables the local input/output line sense amplifier. Since the semiconductor memory device selectively enables or disables the local input/output line sense amplifier, unnecessary current consumption caused due to dummy sensing is avoided.

Claims25

Dependent claims

A semiconductor memory device which selectively controls a local input/output line sense amplifier, wherein the semiconductor memory device comprises:

a memory cell array block, which includes a local input/output line sense amplifier which operates in response to a sense amplifier enable signal;
a redundancy circuit, which includes a redundancy local input/output line sense amplifier which operates in response to the sense amplifier enable signal;
a switch unit, which selectively outputs data output from the local input/output line sense amplifier or the redundancy local input/output line sense amplifier in response to a first select signal and a second select signal;
and
a control unit which generates in response to the second select signal a sense amplifier operation control signal that disables the local input/output line sense amplifier, if the redundancy circuit operates.

2 more elements

A semiconductor memory device which selectively controls a local input/output line sense amplifier, wherein the semiconductor memory device comprises:

an upper memory cell array block, which includes an upper local input/output line sense amplifier which operates in response to an upper sense amplifier enable signal;
an upper redundancy circuit, which includes an upper redundancy local input/output line sense amplifier which operates in response to the upper sense amplifier enable signal;
a lower memory cell array block, which includes a lower local input/output line sense amplifier which operates in response to a lower sense amplifier enable signal;
a lower redundancy circuit, which includes a lower redundancy local input/output line sense amplifier that operates in response to the lower sense amplifier enable signal;
a switch unit, which selectively outputs data output from the upper local input/output line sense amplifier, the upper redundancy local input/output line sense amplifier, or the lower redundancy local input/output line sense amplifier in response to a first select signal, a second upper select signal, and a second lower select signal;
and
a control unit which:
generates, in response to the second upper select signal, an upper sense amplifier operation control signal which disables the upper local input/output line sense amplifier, if the upper redundancy circuit operates;
and
generates, in response to the second lower select signal, a lower sense amplifier operation control signal which disables the lower local input/output line sense amplifier, if the lower redundancy circuit operate.

7 more elements

A semiconductor memory device which selectively controls a local input/output line sense amplifier, the semiconductor memory device comprising:

an upper memory cell array block, which includes an upper local input/output line sense amplifier that operates in response to an upper sense amplifier enable signal;
a redundancy circuit, which includes an upper redundancy local input/output line sense amplifier that operates in response to the upper sense amplifier enable signal;
a lower memory cell array block, which outputs stored data to an input/output line;
a lower redundancy circuit, which includes a lower redundancy local input/output line sense amplifier that operates in response to the lower sense amplifier enable signal;
a switch unit, which selectively outputs data output from the upper local input/output line sense amplifier, the upper redundancy local input/output line sense amplifier, or the lower redundancy local input/output line sense amplifier in response to a first select signal, a second upper select signal, and a second lower select signal;
and
a local input/output line directly connected to the input/output line.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device which selectively controls a local input/output line sense amplifier

Life of this patent

Semiconductor memory device which selectively controls a local input/output line sense amplifier

Life of this patent

Abstract

Claims25