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US 7,002,855 B2Granted
Leakage tolerant register file
AssigneeIntel Corporation
InventorsSapumal Wijeratne, Pankaj Aswal, Mohammad M. Haq, Marijan Persun
Life of this patent
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Abstract
A register file includes a dynamic local bit trace, a plurality of data cells coupled to the dynamic local bit trace, and a device coupled to the dynamic local bit trace to facilitate precharging the dynamic local bit trace to a precharge value and to intelligently hold the precharged value on the dynamic local bit trace during evaluation of the dynamic local bit trace.
Claims34
A register file comprising:
- a dynamic local bit trace;
- a plurality of data cells coupled to the dynamic local bit trace;
- and
- a device coupled to the dynamic local bit trace to facilitate precharging the dynamic local bit trace to a precharge value and to intelligently hold the precharged value on the dynamic local bit trace during evaluation of the dynamic local bit trace.
1 more element
A register file comprising:
- a dynamic local bit trace;
- a plurality of data cells coupled to the dynamic local bit trace;
- and
- a device coupled to the dynamic local bit trace to facilitate precharging the dynamic local bit trace to a precharge value and to selectively couple and decouple a driving signal trace from the dynamic local bit trace to hold the precharged value on the dynamic local bit trace during evaluation of the dynamic local bit trace.
1 more element
A register file comprising:
- a dynamic local bit trace;
- a precharge device coupled to the dynamic local bit trace;
- a plurality of data cells coupled to the dynamic local bit trace;
- and
- a device coupled to the dynamic local bit trace to intelligently hold a precharged value on the dynamic local bit trace.
2 more elements
A register file comprising:
- a first and a second dynamic local bit trace;
- a first and a second plurality of data cells correspondingly coupled to the first and the second dynamic local bit traces;
- a first and a second device correspondingly coupled to the first and the second dynamic local bit traces to facilitate precharging the first and the second dynamic local bit traces to a precharge value and to intelligently hold the precharged value on the first and the second dynamic local bit traces during evaluation of the first and the second dynamic local bit traces;
- and
- global multiplexing logic coupled to the first and the second dynamic local bit traces to facilitate provision of a data value corresponding to an accessed data cell on an output signal trace.
2 more elements
A system comprising:
- a processor including;
- a register file comprising:
- a first and a second dynamic local bit trace;
- a first and a second plurality of data cells correspondingly coupled to the first and the second dynamic local bit traces;
- a first and a second device correspondingly coupled to the first and the second dynamic local bit traces to facilitate precharging the first and the second dynamic local bit traces to a precharge value and to intelligently hold the precharged value on the first and the second dynamic local bit traces during evaluation of the first and the second dynamic local bit traces;
- and
- global multiplexing logic coupled to the first and the second dynamic local bit traces to facilitate provision of a data value corresponding to an accessed data cell on an output signal trace;
- a memory configured to store data;
- and
- a bus coupled to the processor and memory to facilitate data exchange between the processor and memory.
7 more elements
Dependencies are inferred from the claim text.