Memory card having a buffer memory for storing testing instruction

A nonvolatile memory apparatus comprising:

• a program ROM;
• a control circuit;
• a volatile memory;
• and
• a nonvolatile memory,
• wherein said program ROM stores a first program which includes a data writing program,
• wherein said nonvolatile memory is capable of storing file data executed said data writing program by said control circuit in response to a first command indicating a data writing function, and stores a second program therein, and
• wherein said control circuit controls reading out of said second program to said volatile memory for operating a communication function in response to a second command.

A nonvolatile memory apparatus comprising:

• a random access memory;
• a read only memory;
• a nonvolatile memory;
• a central processing unit;
• and
• an address table,
• wherein said read only memory comprises a first program step for performing a first operation of the nonvolatile memory apparatus therein in accordance with a first command received from outside of the nonvolatile memory apparatus,
• wherein said nonvolatile memory is capable of storing data and is capable of storing a second program step, which second program step is for performing a second operation of the nonvolatile memory apparatus therein,
• wherein said random access memory is capable of storing said second program step read out from said nonvolatile memory,
• wherein said address table indicates an allocated address of said second program step in said random access memory,
• wherein said central processing unit executes said first program step when said first command is received, and
• wherein said central processing unit fetches said allocated address of said second program step from said address table and executes said second program step, when a command in accordance with said second operation is received from outside of the nonvolatile memory apparatus.

A nonvolatile memory apparatus comprising:

• a random access memory;
• a read only memory;
• a nonvolatile memory;
• a central processing unit;
• and
• an address table,
• wherein said read only memory comprises first operation steps for performing a first operation of the nonvolatile memory apparatus therein in accordance with a first command received from outside of the nonvolatile memory apparatus,
• wherein said nonvolatile memory is capable of storing data,
• wherein said random access memory is capable of storing second operation steps,
• wherein said address table indicates an allocated address of said second operation steps in said random access memory,
• wherein said central processing unit executes said first operation steps when said first command is received, and
• wherein said central processing unit fetches said allocated address of said second operation steps from said address table and executes said second operation steps, when a command in accordance with said second operation is received from outside of the nonvolatile memory apparatus therein.

A nonvolatile memory apparatus comprising:

• a read only memory;
• a random access memory;
• a nonvolatile memory;
• a processing unit;
• and
• an address table,
• wherein said read only memory stores first program steps,
• wherein said nonvolatile memory is capable of storing data and is capable of storing second program steps,
• wherein said random access memory is capable of storing said second program steps read out from said nonvolatile memory,
• wherein said address table comprises a plurality of entries, wherein a first entry of said plurality of entries stores a first allocated address which indicates an allocated address of said first program steps in said read only memory, and wherein a second entry of said plurality of entries stores a second allocated address which indicates an allocated address of said second program steps in said random access memory,
• wherein said processing unit decodes a command received from outside, and fetches said first allocated address from said first entry of said plurality of entries when said processing unit performs a first operation in accordance with said first program steps, or fetches said second allocated address from said second entry of said plurality of entries when said processing unit performs a second operation in accordance with said second program steps.

A nonvolatile memory apparatus comprising:

• a nonvolatile memory array having a plurality of memory cells, each of which is capable of data erasing electrically and is capable of data programming electrically;
• a volatile memory having a first memory area and a second memory area;
• and
• a control circuit having a program memory,
• wherein said control circuit is capable of performing arbitary one of operations in response to a received command by excuting operation steps,
• wherein in a read operation in response to receiving a read command, by excuting first operation steps for performing said read operation read out from said program memory, said control circuit controls to reading a first data from ones of said plurality of memory cells of said nonvolatile memory array, storing said first data into said first memory area of said volatile memory, and outputting said first data stored into said first memory area,
• wherein a write operation in response to receiving a write command, by excuting second operation steps for performing said write operation read out from said program memory, said control circuit controls to receiving second data, storing said second data into said first memory area of said volatile memory, and writing said second data into ones of said plurality of memory cells of said nonvolatile memory array, and
• wherein said control circuit executes third operation steps for performing a first operation read out from said second memory area of said volatile memory.

A nonvolatile memory apparatus comprising:

• a nonvolatile memory array;
• a control circuit coupled to said nonvolatile memory array by an input/output signal line, and a command enable signal line, said input/output signal line is used for data inputting/outputting, an address inputting, and a command inputting;
• and said command enable signal line is used for indicating whether command inputting has occurred or not via said input/output signal line;
• a volatile memory having a first memory area and a second memory area;
• and
• a plurality of terminals having a data input/output terminal, a command input terminal, and a clock terminal, wherein said data input/output terminal is used for data inputting or data outputting, said command input terminal is used for host command inputting and command response outputting, and said clock terminal is used for clock signal inputting,
• wherein said control circuit has a program memory, which is structured as a nonvolatile memory, and performs a first operation by excuting first operation steps stored in said program memory,
• wherein said nonvolatile memory is capable of storing data and a second operation steps,
• wherein said control circuit performs said first operation in accordance with a first command received from said command input terminal as a host command for accessing data of said nonvolatile memory via memory area of said volatile memory,
• wherein said control circuit performs a second operation by excuting said second operation steps read from said second memory area of said volatile memory, and
• wherein said control circuit reads out said second operation steps from said nonvolatile memory to said second memory area of said volatile memory before performing said second operation via said input/output signal line.