US 7,002,850 B2 · System and method for over erase reduction of nitride read only memory

Abstract

A nitride read only memory (NROM) erase system is disclosed. The NROM erase system comprises at least one memory sector, N sense amplifiers, and N buffers. The memory sector is segmented into N erase retry units according to the number of the sense amplifiers. One buffer corresponds with one erase retry unit and one sense amplifier. The N buffers are used to indicate whether their corresponding erase retry units are erased after an erase process of an erase operation. One of the buffers will be set if its corresponding erase retry unit is not erased. In this case, a subsequent erase process will begin to erase the un-erased erase retry unit. The erase retry units that are erased in a previous erase process will not be affected by the subsequent erase process. A method for using the disclosed NROM erase system is also described.

Claims28

Dependent claims

A system for reducing over-erased memory cells, comprising:

N sense amplifiers, N being an integer;
at least one memory sector segmented by the N sense amplifiers into N erase retry units with one erase retry unit of the memory sector corresponding with one sense amplifier, the memory sector having a starting address and an ending address, at most K erase retry units can be erased concurrently during an erase process of an erase operation, K being an integer and being less than or equal to N;
and
at least N buffers for showing whether any of the N erase retry units of the memory sector are erased after the erase process of the erase operation, the N buffers corresponding with the N erase retry units and the N sense amplifiers with at least one buffer corresponding with one erase retry unit of the memory sector and one sense amplifier, the erase process of the erase operation being followed by a verification process of the erase operation, the erase operation including at least one erase process and at least one verification process.

1 more element

A method for reducing over-erased memory cells, comprising:

selecting a memory sector to be erased;
dividing the memory sector into N erase retry units according to number of sense amplifiers, N being an integer, at least N buffers corresponding with the N erase retry units and the sense amplifiers, one erase retry unit of the memory sector corresponding with one sense amplifier and at least one buffer, the memory sector having a starting address and an ending address;
resetting all of the N buffers;
erasing un-erased erase retry units of the memory sector by an erase voltage pulse during an erase process of an erase operation, the erase voltage pulse is only applied to the un-erased erase retry units;
verifying whether any un-erased erase retry units exist during a verification process of the erase operation, if un-erased erase retry units still exist after the erase process of the erase operation, their corresponding buffers will be set;
checking the buffers to see whether any of the buffers is set;
increasing the erase voltage pulse slightly if any buffers are set;
and
iterating the resetting step to the increasing step until all of the N erase retry units are erased.

6 more elements

Dependencies are inferred from the claim text.

System and method for over erase reduction of nitride read only memory

Life of this patent

System and method for over erase reduction of nitride read only memory

Life of this patent

Abstract

Claims28