US 7,002,848 B2 · Nonvolatile semiconductor memory device

Abstract

This is a nonvolatile semiconductor memory device capable of raising the speed of write operation of Y access circuits in a 1×sense latch circuit+2×SRAM configuration. In a multi-value flash memory, in a mode of writing from the lower voltage side, writing and erratic determination are performed after data are transferred from SRAMs to a sense latch circuit for “10” and “00” distributions; after the data transfer for “01” distribution, writing is done; after the data transfer for “11” distribution word disturb determination is done; and simplified upper limit determination is done in this sequence. In particular by (1) writing from the lower voltage side of the threshold voltage distribution in the multi-value memory and (2) consecutive application of “write processing” and “upper limit determination processing” to each threshold voltage distribution, after the end of write processing for “10” and “00” distribution, since the threshold voltages of all the memory cells are lower than the upper limit determination voltages of the “10” and “00” distributions, no transfer of write data is needed in upper limit determination processing because other threshold voltage distributions are not masked.

Claims12

Dependent claims

A nonvolatile semiconductor memory device, comprising:

a plurality of word lines;
a plurality of bit lines;
a plurality of memory cells each connected to a corresponding word line and a corresponding bit line and having a control gate and a floating gate;
and
a memory array having each of said plurality of memory cells so configured as to be able to store data of a plurality of bits as threshold voltages,
wherein said nonvolatile semiconductor memory device includes a write mode in which write operation is performed for moving the threshold voltage of the memory cells to be written within the side of a lower threshold voltage distribution, and upper limit determination processing to confirm that no excessive writing of each threshold voltage distribution is performed for all the memory cells, and write processing of the following threshold voltage distribution is started, and
wherein said write processing and said upper limit determination processing are consecutively applied to each threshold voltage distribution.

4 more elements

A nonvolatile semiconductor memory device comprising:

a plurality of word lines;
a plurality of bit lines;
a plurality of memory cells each connected to a corresponding word line and a corresponding bit line and having a control gate and a floating gate;
and
a memory array including each of said plurality of memory cells so configured as to be able to store data of a plurality of bits as threshold voltages,
wherein said nonvolatile semiconductor memory device comprises a write mode in which write processing is performed for moving threshold voltage of memory cell within a level n threshold voltage distribution and within a level n+1 threshold voltage distribution, read processing is performed at an upper limit determination voltage level of said level n threshold voltage distribution and a read voltage level of said level n threshold voltage distribution without discriminating any of the memory cells from others, and the existence of no memory cell having a threshold voltage distribution between said upper limit determination voltage level and said read voltage level is determined, the write mode including upper limit determination processing to confirm that no excessive writing is done.

3 more elements

Dependencies are inferred from the claim text.

Nonvolatile semiconductor memory device

Life of this patent

Nonvolatile semiconductor memory device

Life of this patent

Abstract

Claims12