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US 7,002,835 B2Granted
Memory cell and semiconductor memory device
AssigneeSeiko Epson Corporation
InventorKenya Watanabe
Life of this patent
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Abstract
Aspects of the invention can prevent delay in output timing of inverted data for each of ferroelectric capacitors, there can be provided NMOSs that can electrically connect upper electrodes of the ferroelectric capacitor with a plate line and electrically connect lower electrodes of the ferroelectric capacitor with bit lines. Further there can be provided NMOSs that can electrically connect the lower electrodes of the ferroelectric capacitor with the plate line, and electrically connect the upper electrodes of the ferroelectric capacitor with bit lines.
Claims7
A memory cell, comprising:
- a ferroelectric capacitor;
- a first connection device that is capable of realizing a first state in which a first electrode of the ferroelectric capacitor is electrically coupled to a plate line and a second electrode of the ferroelectric capacitor is electrically coupled to a bit line;
- and
- a second connection device that is capable of realizing a second state in which the second electrode of the ferroelectric capacitor is electrically coupled to the plate line and the first electrode of the ferroelectric capacitor is electrically coupled to the bit line,
- the first state, the second state, or a state in which the first electrode and the second electrode are not coupled to either the plate line or the bit line can be selected.
2 more elements
Dependencies are inferred from the claim text.