Magnetic semiconductor memory device
AssigneeRenesas Technology Corp.
InventorsHideyuki Matsuoka, Kenchi Ito, Takeshi Sakata, Kiyoo Itoh
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Abstract
A memory cell in a so-called MRAM by utilizing a tunnel magnetic resistance in the prior art has raised problems that a magnetic field to be applied to a TMR element is essentially weak since a word line for write is disposed apart from the TMR element, that a large current is required at the time of a writing operation, and that electric power consumption is large. In order to solve the above-described problems experienced in the prior art, the present invention provides an MRAM memory cell structure and its fabricating method in which a word line for write is disposed near a TMR element and surrounds it in three directions.
Claims19
A magnetic semiconductor memory device comprising:
- a semiconductor substrate;
- first and second word lines arranged in parallel to each other on the semiconductor substrate;
- first and second bit lines crossing the first and second word lines via an insulator layer;
- and
- a first memory cell including a first transistor controlled by the first word line and a first magnetic resistance element disposed between the first transistor and the first bit line;
- a second memory cell including a second transistor controlled by the first word line and a second magnetic resistance element disposed between the second transistor and the second bit line;
- wherein each of the first and second magnetic resistance elements is formed into a pillar-like shape by patterning a plurality of layered structures formed on the semiconductor substrate, and at least the side surface is covered with the second word line via the insulator layer,
- wherein the magnetic semiconductor memory device further comprises a gap between a first part of the second word line along a side surface of the first magnetic resistance element and a second part of the second word line along a side surface of the second magnetic resistance element.
A magnetic semiconductor memory device comprising:
- a semiconductor substrate;
- first and second word lines arranged in parallel to each other on the semiconductor substrate;
- first and second bit lines crossing the first and second word lines via an insulator layer;
- a first memory cell including a first transistor controlled by the first word line and a first magnetic resistance element disposed between the first transistor and the first bit line;
- and
- a second memory cell including a second transistor controlled by the first word line and a second magnetic resistance element disposed between the second transistor and the second bit line;
- wherein each of the first and second magnetic resistance elements is formed into a pillar-like shape by patterning a plurality of layered structures formed on the semiconductor substrate, and the top surface and two side surfaces are covered with the second word line via the insulator layer,
- wherein the magnetic semiconductor memory device further comprises a gap between a first part of the second word line along one of the side surfaces of the first magnetic resistance element and a second part of the second word line along one of the side surfaces of the second magnetic resistance element.
A magnetic semiconductor memory device comprising:
- a semiconductor substrate;
- a plurality of word lines formed on the semiconductor substrate;
- a plurality of bit lines crossing the plurality of word lines;
- and
- a memory array including memory cells arranged at crossing points between the plurality of word lines and the plurality of bit lines and including a first memory cell and a second memory cell;
- wherein each of the memory cells includes a vertical type transistor having a channel area formed in a direction perpendicular to the main surface of the semiconductor substrate and having a magnetic resistance element disposed above the vertical type transistor, corresponding one of the plurality of word lines being a gate electrode of the vertical type transistor and covering at least two side surfaces of the magnetic resistance element via an insulator film,
- wherein gate electrodes of the vertical type transistors included in the first and second memory cells are associated with the same word line,
- wherein there is a gap between a first part of the same word line along one side surface of the magnetic resistance element of the first memory cell and a second part of the same word line along one side surface of the magnetic resistance element of the second memory cell.
Dependencies are inferred from the claim text.