Methods and apparatuses for a ROM memory array having a virtually grounded line
AssigneeVirage Logic Corporation
InventorsDeepak Sabharwal, Izak Kense, Alexander Shubat
Life of this patent
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Abstract
Methods and apparatuses in which a ROM memory array has virtual-grounded source lines programmed in layer physically higher than the diffusion layer. The ROM memory array may include a diffusion layer, one or more virtual-grounded source lines, and one or more bit lines. At least one of the virtual-grounded source lines is programmed with a layer physically higher than the diffusion layer.
Claims18
An apparatus, comprising:
- a ROM memory array having a diffusion layer, one or more virtual-grounded source lines, and one or more bit lines, wherein the ROM memory array includes an array of rows of bit cells and columns of bit cells, each column of bit cells arranged so source terminals and drain terminals for two or more bit cells in a bit cell column are shared along the bit cell column, and wherein at least one or more of the virtual-grounded source lines are programmed with a layer physically higher than the diffusion layer.
A machine readable medium that stores data representing an integrated circuit, comprising:
- a ROM memory array having a diffusion layer, one or more virtual-grounded source lines, and one or more bit lines, wherein at least one or more of the virtual-grounded source lines are programmed in a layer physically higher than the diffusion layer and wherein the ROM memory array includes a first column of bit cells that includes a first bit cell, a second bit cell and a third bit cell, wherein the first bit cell shares its source terminal with the second bit cell and its drain terminal with the third bit cell.
A ROM memory array having a diffusion layer, one or more virtual grounded source lines, one or more bit lines, and a switch to delay switching off a precharge voltage supplied to a first bit line in order to reduce coupling noise from an adjacent virtual-grounded source line, wherein at least one or more of the virtual-grounded source lines are programmed with a layer physically higher than the diffusion layer.
A ROM memory array having a diffusion layer, one or more virtual-grounded source lines, and one or more bit lines, wherein at least one or more of the virtual-grounded source lines are programmed with a layer physically higher than the diffusion layer and the one or more bit lines include a first bit line that is formed from at least two conductive strips with multiple interconnections between the strips.
Dependencies are inferred from the claim text.