Semiconductor memory device
AssigneeRenesas Technology Corp.
InventorKoji Nii
Life of this patent
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Abstract
A semiconductor memory device having a multiport memory includes a plurality of memory cells MC arranged in columns and rows, a plurality of first word lines WLA0-WLAn connected to a first port 13a, and a plurality of second word lines WLB0-WLBn connected to a second port 13b. Each of a plurality of first word lines WLA0-WLAn and each of a plurality of second word lines WLB0-WLBn are arranged alternately in a planar layout. A semiconductor memory device is thus obtained that allows a coupling noise between interconnections to be reduced without an increase in memory cell area.
Claims4
A semiconductor memory device, comprising:
- a first word line selected by an address signal from a first port having a first input/output group;
- a second word line selected by an address signal from a second port having a second input/output group;
- and
- a memory cell array in which a plurality of memory cells are arranged in columns and rows, said memory cells each including a first region in which a first transistor of a first conductivity type connected to said first word line is formed, a second region arranged adjacent to said first region in a row direction toward which said first and second word lines extend, and in which a transistor of a second conductivity type is formed, and a third region arranged adjacent to said second region in said row direction and in which a second transistor of said first conductivity type connected to said second word line is formed;
- wherein
- between a first memory cell and a second memory cell adjacent to each other in a column direction of said memory cell array, a distance between said second word line connected to said first memory cell and said second word line connected to said second memory cell is longer than a distance between said second word line connected to said first memory cell and said first word line connected to said second memory cell.
A semiconductor memory device, comprising
- a memory cell array having a plurality of memory cells arranged in columns and rows, wherein
- each of said memory cells has a first region in which a first transistor of a first conductivity type is formed, a second region in which a second transistor of said first conductivity type is formed, and a third region interposed between said first region and said second region and in which a transistor of a second conductivity type is formed,
- a first word line selected from a first port outputting a first address signal is connected to said first transistor, a second word line selected from a second port outputting a second address signal is connected to said second transistor, and
- between respective first word lines of said memory cells adjacent to each other in a column direction, said second word line connected to one memory cell is interposed, and said second word line connected to other memory cell is non-interposed.
Dependencies are inferred from the claim text.