Failsafe display of frame locked graphics
AssigneePixelworks, Inc.
InventorsMichael G. West, Jamie J. LeVasseur
Life of this patent
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Abstract
A system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor. The system receives input image data at an input frame rate and/or input resolution. The packing circuit generates coded image data by compressing the input image data. An unpacking circuit decompresses the coded image and provides output image data to a display device at an output frame rate and/or output resolution.
Claims26
A display system adapted to display input image data received one frame at a time at an input frame rate and an input resolution on a display having an output frame rate and an output resolution, comprising:
- a pixel packing circuit adapted to generate coded image data responsive to a failsafe enable signal, the coded image data being a compressed representation of the input image data including a plurality of pixel bits and a palette bit, the palette bit to select one of a plurality of levels in a color palette for representing each of the pixel bits;
- and
- a pixel unpacking circuit adapted to generate output image data capable of being displayed on the display by manipulating the coded image data responsive to the palette bit.
A system for visually displaying digital images, comprising:
- input image signals provided to the system one frame at a time, the input image signals having input characteristics;
- a display capable of displaying output image signals having output characteristics;
- a failsafe enable adapted to identify when the input characteristics exceeds the output characteristics;
- a packing circuit adapted to generate a coded signal by compressing the input image signals responsive to the failsafe enable, the coded signal including a plurality of pixel bits and a palette bit, the palette bit being adapted to select one of a plurality of levels in a color palette for representing each of the pixel bits;
- a memory adapted to store the coded signal;
- and
- an unpacking circuit adapted to generate the output image signals at the output characteristics by logically manipulating the coded signal responsive to the palette bit.
A failsafe circuit, comprising:
- an input pixel formatter circuit adapted to receive input signals at an input frame rate and an input resolution representative of an image and adapted to generate a coded signal representing a compressed version of the image, the coded signal including a plurality of pixel bits and a palette bit to select one of a plurality of levels in a palette;
- a memory buffer adapted to store the coded signal;
- and
- a pixel value generator circuit adapted to generate output signals by manipulating the coded signals responsive to the palette bit.
A method for automatically displaying digital image data having an input frame rate on a display having an output frame rate, comprising:
- enabling a failsafe signal if the input frame rate exceeds the output frame rate;
- compressing the image data responsive to the failsafe signal, the compressed image data including a palette bit to select one of a plurality of levels in a palette;
- displaying the compressed image data;
- and
- allowing a user to change display settings after displaying the compressed image data.
Dependencies are inferred from the claim text.