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US 7,002,564 B1Granted
Failsafe display of frame locked graphics
AssigneePixelworks, Inc.
InventorRobert Y. Greenberg
Life of this patent
Estimating the term…
Abstract
The invention describes a system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor. The system receives input image data at an input vertical refresh rate and displays the image data at a vertical refresh rate that is a predetermined fraction of the input vertical refresh rate.
Claims16
A display controller adapted to display image data received at an input vertical refresh rate on a display having a display vertical refresh rate, comprising:
- a failsafe enable circuit to generate a failsafe enable signal responsive to the input vertical refresh rate;
- and
- a failsafe circuit to generate an internal vertical refresh rate responsive to the failsafe enable signal, the internal vertical refresh rate being a predetermined fraction of the input vertical refresh rate;
- where the system controller operates responsive to one of a plurality of modes comprising:
- a display first mode where a first frame of the image data is displayed on the display while other frames are discarded in a single output frame;
- a display last mode where a last frame of the image data is displayed on the display while other frames are discarded in the single output frame;
- a display all mode where all frames of the image data are displayed on the single output frame.
4 more elements
A system for visually displaying digital images, comprising:
- image signals provided to the system one frame at a time, the image signals having an input vertical refresh rate;
- a display capable to display the image signals having a display vertical refresh rate;
- a failsafe enable to identify when the input vertical refresh rate exceeds the display vertical refresh rate and generate an enable signal responsive to the identification;
- a failsafe circuit to generate an internal vertical refresh rate a predetermined fraction of the input vertical refresh rate responsive to the enable signal;
- where the internal vertical refresh rate is half the input vertical refresh rate;
- where the failsafe circuit comprises:
- a display first mode where a first input frame is displayed on a single output frame while a second input frame is discarded;
- a display last mode where the second input frame is displayed on the single output frame while the first input frame is discarded;
- and
- display both mode where both the first and second input frames are displayed on the single output frame.
7 more elements
A failsafe circuit comprising:
- a flip-flop adapted to generate a first signal responsive to an input vertical refresh rate;
- an inverter adapted to invert the first signal;
- a logic gate adapted to generate an internal vertical refresh rate by logically manipulating the first signal and the input vertical refresh rate, the internal vertical refresh rate being a factor of the input vertical refresh rate;
- a multiplexer adapted to select the internal vertical refresh rate responsive to the enable signal;
- and
- a mode circuit adapted to generate a mode signal responsive to user input indicative of one of a plurality of modes;
- wherein plurality of modes, comprises:
- a display first mode wherein a first frame is received during a predetermined interval is displayed on a single output frame while other frames received during the predetermined time interval are discarded;
- a display last mode where a last frame received during a predetermined time interval is displayed on the single output frame while other frames received during the predetermined time interval are discarded;
- and
- a display all mode where all frames received during the predetermined time interval are displayed on the single output frame.
8 more elements
A system for visually displaying digital images, comprising:
- a display to display image signals having a display vertical refresh rate;
- a failsafe enable to identify when the input vertical refresh rate exceeds the display vertical refresh rate and generate an enable signal responsive to the identification;
- a failsafe circuit to generate an internal vertical refresh rate a predetermined fraction of the input vertical refresh rate responsive to the enable signal;
- where the failsafe circuit operates in at least one of:
- a display first mode where a first input frame is displayed on a single output frame while a second input frame is discarded;
- a display last mode where the second input frame is displayed on the single output frame while the first input frame is discarded;
- or
- display both mode where both the first and second input frames are displayed on the single output frame.
5 more elements
Dependencies are inferred from the claim text.