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US 7,002,545 B2Granted
Shift register and method of driving the same
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorMitsuaki Osame
Life of this patent
Estimating the term…
Abstract
A clock pulse with a smaller amplitude voltage than the power supply voltage of the shift register is inputted to the shift register. The gate width of a TFT that constitutes a second clocked inverter of the shift register is set wide so as to reduce fluctuation in output electric potential due to leak current of a first clocked inverter. Further, a TFT is added to a first clocked inverter. A signal with an amplitude voltage of the same level as the power supply voltage is inputted to a gate electrode of the added TFT to switch between ON and OFF. The leak current of the first clocked inverter is thus cut off.
Claims36
A shift register comprising r (r is a natural number equal to or larger than 3) stages each comprising:
- first and second clocked inverters that each outputs a signal in sync with a clock pulse and an inverted clock pulse obtained by inverting the polarity of the clock pulse;
- and
- means for inputting to the second clocked inverter a signal obtained by inverting the polarity of an output signal from the first clocked inverter,
- wherein at least one of the r stages outputs pulse signals in sync with clock pulse signals serially,
- wherein an amplitude voltage of the clock pulse signal is smaller than a power supply voltage of the r stages,
- wherein an output terminal of the first clocked inverter is connected to an output terminal of the second clocked inverter,
- wherein, in a k-th (k is a natural number equal to or larger than 3, and equal to or smaller than r) stage, a wiring line kept at a first power supply electric potential of the first clocked inverter is connected to the output terminal of the first clocked inverter through a first n-channel TFT and a second n-channel TFT connected in series to the first n-channel TFT,
- wherein a signal obtained by inverting the polarity of a signal outputted from the first clocked inverter of the (k−1)-th stage is inputted to a gate electrode of the first n-channel TFT,
- wherein the output terminal of the first clocked inverter of the (k−2)-th stage is connected to a gate electrode of the second n-channel TFT, and
- wherein pulse signals outputted from the (k−1)-th stage and pulse signals outputted from the (k−2)-th stage are inputted to the k-th stage.
7 more elements
A shift register comprising r (r is a natural number equal to or larger than 3) stages each comprising:
- first and second clocked inverters that each outputs a signal in sync with a clock pulse and an inverted clock pulse obtained by inverting the polarity of the clock pulse;
- and
- means for inputting to the second clocked inverter a signal obtained by inverting the polarity of an output signal from the first clocked inverter,
- wherein at least one of the r stages outputs pulse signals in sync with clock pulse signals serially,
- wherein an amplitude voltage of the clock pulse signal is smaller than a power supply voltage of the r stages,
- wherein an output terminal of the first clocked inverter is connected to an output terminal of the second clocked inverter,
- wherein, in the j-th (j is a natural number equal to or larger than 2, and equal to or smaller than r) stage, a wiring line kept at a first power supply electric potential of the first clocked inverter is connected to the output terminal of the first clocked inverter through a first n-channel TFT and a second n-channel TFT connected in series to the first n-channel TFT,
- wherein a signal obtained by inverting the polarity of a signal outputted from the first clocked inverter of the (j−1)-th stage is inputted to a gate electrode of the first n-channel TFT,
- wherein, in the second stage, a gate electrode of the second n-channel TFT is connected to the output terminal of the first clocked inverter of the first stage through a delay circuit,
- wherein, in the k-th (k is a natural number equal to or larger than 3 and equal to or smaller than r) stage, the output terminal of the first clocked inverter of the (k−2)-th stage is connected to a gate electrode of the second n-channel TFT, and
- wherein pulse signals outputted from the (k−1)-th stage and pulse signals outputted from the (k−2)-th stage are inputted to the k-th stage.
8 more elements
A shift register comprising r (r is a natural number equal to or larger than 3) stages each comprising:
- first and second clocked inverters that each outputs a signal in sync with a clock pulse and an inverted clock pulse obtained by inverting the polarity of the clock pulse;
- and
- means for inputting to the second clocked inverter a signal obtained by inverting the polarity of an output signal from the first clocked inverter,
- wherein at least one of the r stages outputs pulse signals in sync with clock pulse signals serially,
- wherein an amplitude voltage of the clock pulse signal is smaller than a power supply voltage of the r stages,
- wherein an output terminal of the first clocked inverter is connected to an output terminal of the second clocked inverter,
- wherein, in the k-th (k is a natural number equal to or larger than 3, and equal to or smaller than r) stage, a wiring line kept at a second power supply electric potential of the first clocked inverter is connected to the output terminal of the first clocked inverter through a first p-channel TFT and a second p-channel TFT connected in series to the first p-channel TFT,
- wherein a signal obtained by inverting the polarity of a signal outputted from the first clocked inverter of the (k−1)-th stage is inputted to a gate electrode of the first p-channel TFT,
- wherein the output terminal of the first clocked inverter of the (k−2)-th stage is connected to a gate electrode of the second p-channel TFT, and
- wherein pulse signals outputted from the (k−1)-th stage and pulse signals outputted from the (k−2)-th stage are inputted to the k-th stage.
7 more elements
A shift register comprising r (r is a natural number equal to or larger than 3) stages each comprising:
- first and second clocked inverters that each outputs a signal in sync with a clock pulse and an inverted clock pulse obtained by inverting the polarity of the clock pulse;
- and
- means for inputting to the second clocked inverter a signal obtained by inverting the polarity of an output signal from the first clocked inverter,
- wherein at least one of the r stages outputs pulse signals in sync with clock pulse signals serially,
- wherein an amplitude voltage of the clock pulse signal is smaller than a power supply voltage of the r stages,
- wherein an output terminal of the first clocked inverter is connected to an output terminal of the second clocked inverter,
- wherein, in the j-th (j is a natural number equal to or larger than 2, and equal to or smaller than r) stage, a wiring line kept at a second power supply electric potential of the first clocked inverter is connected to the output terminal of the first clocked inverter through a first p-channel TFT and a second p-channel TFT connected in series to the first p-channel TFT,
- wherein a signal obtained by inverting the polarity of a signal outputted from the first clocked inverter of the (j−1)-th stage is inputted to a gate electrode of the first p-channel TFT,
- wherein, in the second stage, a gate electrode of the second p-channel TFT is connected to the output terminal of the first clocked inverter of the first stage through a delay circuit,
- wherein, in the k-th (k is a natural number equal to or larger than 3 and equal to or smaller than r) stage, the output terminal of the first clocked inverter of the (k−2)-th stage is connected to a gate electrode of the second p-channel TFT, and
- wherein pulse signals outputted from the (k−1)-th stage and pulse signals outputted from the (k−2)-th stage are inputted to the k-th stage.
8 more elements
A shift register comprising r (r is a natural number equal to or larger than 3) stages each comprising first and second clocked inverters and an inverter,
- wherein at least one of the r stages outputs pulse signals in sync with clock pulse signals serially,
- wherein an amplitude voltage of the clock pulse signal is smaller than a power supply voltage of the r stages,
- wherein an output terminal of the first clocked inverter is connected to an output terminal of the second clocked inverter,
- wherein the output terminal of the first clocked inverter is connected to an input terminal of the inverter,
- wherein, in the k-th (k is a natural number equal to or larger than 3, and equal to or smaller than r) stage, a wiring line kept at a first power supply electric potential of the first clocked inverter is connected to the output terminal of the first clocked inverter through a first n-channel TFT and a second n-channel TFT connected in series to the first n-channel TFT,
- wherein a gate electrode of the first n-channel TFT is connected to an output terminal of the inverter of the (k−1)-th stage,
- wherein the output terminal of the first clocked inverter of the (k−2)-th stage is connected to a gate electrode of the second n-channel TFT, and
- wherein pulse signals outputted from the (k−1)-th stage and pulse signals outputted from the (k−2)-th stage are inputted to the k-th stage.
5 more elements
A shift register comprising r (r is a natural number equal to or larger than 3) stages each comprising first and second clocked inverters and an inverter,
- wherein at least one of the r stages outputs pulse signals in sync with clock pulse signals serially,
- wherein an amplitude voltage of the clock pulse signal is smaller than a power supply voltage of the r stages,
- wherein an output terminal of the first clocked inverter is connected to an output terminal of the second clocked inverter,
- wherein the output terminal of the first clocked inverter is connected to an input terminal of the inverter,
- wherein, in the j-th (j is a natural number equal to or larger than 2, and equal to or smaller than r) stage, a wiring line kept at a first power supply electric potential of the first clocked inverter is connected to the output terminal of the first clocked inverter through a first n-channel TFT and a second n-channel TFT connected in series to the first n-channel TFT,
- wherein a gate electrode of the first n-channel TFT is connected to an output terminal of the inverter of the (j−1)-th stage,
- wherein, in the second stage, a gate electrode of the second n-channel TFT is connected to the output terminal of the first clocked inverter of the first stage through a delay circuit,
- wherein, in the k-th (k is a natural number equal to or larger than 3 and equal to or smaller than r) stage, the output terminal of the first clocked inverter of the (k−2)-th stage is connected to a gate electrode of the second n-channel TFT, and
- wherein pulse signals outputted from the (k−1)-th stage and pulse signals outputted from the (k−2)-th stage are inputted to the k-th stage.
6 more elements
A shift register comprising r (r is a natural number equal to or larger than 3) stages each comprising first and second clocked inverters and an inverter,
- wherein an output terminal of the first clocked inverter is connected to an output terminal of the second clocked inverter,
- wherein the output terminal of the first clocked inverter is connected to an input terminal of the inverter,
- wherein, in the k-th (k is a natural number equal to or larger than 3, and equal to or smaller than r) stage, a wiring line kept at a second power supply electric potential of the first clocked inverter is connected to the output terminal of the first clocked inverter through a first p-channel TFT and a second p-channel TFT connected in series to the first p-channel TFT,
- wherein a gate electrode of the first p-channel TFT is connected to an output terminal of the inverter of the (k−1)-th stage,
- wherein the output terminal of the first clocked inverter of the (k−2)-th stage is connected to a gate electrode of the second p-channel TFT, and
- wherein pulse signals outputted from the (k−1)-th stage and pulse signals outputted from the (k−2)-th stage are inputted to the k-th stage.
3 more elements
A shift register comprising r (r is a natural number equal to or larger than 3) stages each comprising first and second clocked inverters and an inverter,
- wherein at least one of the r stages outputs pulse signals in sync with clock pulse signals serially,
- wherein an amplitude voltage of the clock pulse signal is smaller than a power supply voltage of the r stages,
- wherein an output terminal of the first clocked inverter is connected to an output terminal of the second clocked inverter,
- wherein the output terminal of the first clocked inverter is connected to an input terminal of the inverter,
- wherein, in the j-th (j is a natural number equal to or larger than 2, and equal to or smaller than r) stage, a wiring line kept at a second power supply electric potential of the first clocked inverter is connected to the output terminal of the first clocked inverter through a first p-channel TFT and a second p-channel TFT connected in series to the first p-channel TFT,
- wherein a gate electrode of the first p-channel TFT is connected to an output terminal of the inverter of the (j−1)-th stage,
- wherein, in the second stage, a gate electrode of the second p-channel TFT is connected to the output terminal of the first clocked inverter of the first stage through a delay circuit,
- wherein, in the k-th (k is a natural number equal to or larger than 3 and equal to or smaller than r) stage, the output terminal of the first clocked inverter of the (k−2)-th stage is connected to a gate electrode of the second p-channel TFT, and
- wherein pulse signals outputted from the (k−1)-th stage and pulse signals outputted from the (k−2)-th stage are inputted to the k-th stage.
6 more elements
A shift register comprising r stages including a k-th stage,
- wherein r is a natural number equal to or larger than 3,
- wherein k is a natural number equal to or larger than 3 and equal to or smaller than r,
- wherein the k-th stage outputs pulse signals in sync with clock pulse signals serially,
- wherein an amplitude voltage of the clock pulse signals is smaller than a power supply voltage of the shift register, and
- wherein pulse signals outputted from a (k−1)-th stage and pulse signals outputted from a (k−2)-th stage are inputted to the k-th stage.
2 more elements
A shift register comprising:
- r stages including a k-th stage;
- a first power supply line supplied with a high power supply electric potential;
- a second power supply line supplied with a low power supply electric potential;
- wherein r is a natural number equal to or larger than 3,
- wherein k is a natural number equal to or larger than 3 and equal to or smaller than r,
- wherein the k-th stage outputs pulse signals in sync with clock pulse signals serially,
- wherein an amplitude voltage of the clock pulse signals is smaller than a potential difference between the high power supply electric potential and the low power supply electric potential,
- wherein the k-th stage comprises:
- a first circuit for selectively outputting one of the high power supply electric potential and the low power supply electric potential from the k-th stage in accordance with the clock pulse signals, first pulse signals outputted from a (k−1)-th stage and second pulse signals outputted from a (k−2)-th stage;
- a second circuit for inverting a polarity of the outputted one of the high power supply electric potential and the low power supply electric potential and outputting the one of high power supply electric potential and the low power supply electric potential of which the polarity has been inverted;
- and
- a third circuit to which the outputted one of the high power supply electric potential and the low power supply electric potential of which the polarity has been inverted is inputted,
- wherein one of the high power supply electric potential and the low power supply electric potential is selectively outputted from the third circuit and inputted to the second circuit.
10 more elements
Dependencies are inferred from the claim text.