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US 7,002,544 B2Granted
Liquid crystal display apparatus operating at proper data supply timing
AssigneeSharp Kabushiki Kaisha
InventorSatoshi Sekido
Life of this patent
Estimating the term…
Abstract
A circuit for driving a liquid crystal display panel includes a plurality of output circuits that are coupled to respective data bus lines of the liquid crystal display panel, and output liquid crystal drive signals to the respective data bus lines with respective delays that progressively increase from a first one of the data bus lines to a last one of the data bus lines.
Claims5
A circuit for driving a liquid crystal display panel, which is to be coupled to and supply display data to data bus lines of the liquid crystal display panel, comprising:
- input nodes which receive the display data and a clock signal;
- registers configured to store the display data as parallel data;
- first output nodes which output the display data stored in said registers to the data bus lines;
- a synchronizing circuit coupled to said registers to convert the display data stored in said registers into serial data synchronized with the clock signal;
- and
- a second output node which supplies the serial data synchronized with the clock signal by said synchronizing circuit to a circuit for driving the liquid crystal display panel provided at a next stage.
3 more elements
A liquid crystal display apparatus, comprising:
- a liquid crystal display panel which includes data bus lines and gate bus lines;
- a plurality of gate drivers which drive the gate bus lines;
- and
- a plurality of data drivers which drive the data bus lines, wherein the data drivers are connected in a cascade connection, and at least one of the data drivers includes:
- input nodes which receive display data and a clock signal;
- registers configured to store the display data as parallel data;
- first output nodes which output the display data stored in said registers to the data bus lines;
- a synchronizing circuit coupled to said registers to convert the display data stored in said registers into serial data synchronized with the clock signal;
- and
- a second output node which supplies the display data synchronized with the clock signal by said synchronizing circuit to a next one of the data drivers provided at a next stage.
7 more elements
Dependencies are inferred from the claim text.