Providing pipe line ADC with acceptable bit error and power efficiency combination

An analog-to-digital converter comprising:

• a first plurality of consecutive flip-around charge redistribution stages, wherein a first one of the first plurality of flip-around charge redistribution stages is configured to receive an input analog signal;
• a plurality of consecutive general charge redistribution stages, wherein a first one of the plurality of consecutive general charge redistribution stages is coupled to a last one of the first plurality of consecutive flip-around charge redistribution stages;
• a second plurality of consecutive flip-around charge redistribution stages, wherein a first one of the second plurality of consecutive flip-around charge distribution stages is coupled to a last one of the plurality of consecutive general charge redistribution stages;
• and
• at least one comparator coupled to a last one of the second plurality of consecutive flip-around charge redistribution stages wherein at least one amplifier in each one of the first and second plurality of consecutive flip-around charge redistribution stages is configured to use a corresponding plurality of capacitors as input capacitors during a sampling phase and as feedback capacitors during a hold phase.

A method of converting an analog signal to a digital signal comprising:

• processing the analog signal in a first plurality of consecutive flip-around charge redistribution stages to generate a first plurality of sub-codes;
• processing output of the first plurality of consecutive flip-around charge redistribution stages in a plurality of consecutive general charge redistribution stages to generate a second plurality of sub-codes;
• processing output of the plurality of consecutive general charge redistribution stages in a second plurality of consecutive flip-around charge redistribution stages to generate a third plurality of sub-codes;
• and
• generating a digital code corresponding to a sample of the analog signal using the first, second, and third plurality of sub-codes,
• wherein at least one amplifier in each one of the first and second plurality of consecutive flip-around charge redistribution stages is configured to use a corresponding plurality of capacitors as input capacitors during a sampling phase and as feedback capacitors during a hold phase.