Switched-current analogue-to-digital converter
AssigneeKoninklijke Philips Electronics N.V.
InventorJohn B. Hughes
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AssigneeKoninklijke Philips Electronics N.V.
InventorJohn B. Hughes
Estimating the term…
An current mode analogue-to-digital converter uses a conversion stage which operates using a two-phase clock and which requires the input signal to be present during only one of the phases. A sample-and-hold circuit (120, 130, 135) samples the input signal during the first clock phase and during the second clock phase a quantised bit value is generated from a mirror of the held input current by a kickback-free comparator circuit (140). Also during the second clock phase a residue is generated using the quantised value and a non-mirrored version of the held input current. Optionally, two comparator circuits (140, 140″) may be used to provide two-level quantisation, enabling errors introduced by the current mirror to be corrected by a Redundant Signed Digit algorithm. Two pipelines of conversion stages (Si′, Si″) can be multiplexed to double the conversion rate.
A current mode pipelined analogue-to-digital converter (ADC) comprising a plurality of serially connected conversion stages (Si) wherein at least one conversion stage comprises, a stage input for receiving a current (ri-1) for conversion, a sample-and-hold (S/H) circuit coupled to sample the current at the stage input during a first time period and to hold the sampled current during a second time period, the S/H circuit having first and second outputs, the first output delivering a mirror of the sampled current during the first time period and a mirror of the held current during the second time period and the second output delivering the held current directly during the second time period, a current comparator means having an input coupled to the first output of the S/H circuit for comparing a current at said input with one or more reference currents, a digital output coupled to an output of the current comparator means for producing a digital signal (D) representing the digital conversion performed by the stage, a digital-to-analogue converter (DAC) having an input coupled to the output of the current comparator means, and a summing means having a first input coupled to an output of the DAC, a second input coupled to the second output of the S/H circuit, and an output for delivering a residual current (ri) during the second time period.
Dependencies are inferred from the claim text.