US 7,002,493 B2 · Boolean logic tree reduction circuit

Abstract

A method and apparatus are provided for performing a Boolean logic tree function on all bits of a multiple-bit binary input data word having a plurality of bit positions. Each bit has one of first and second complementary logic states. A modified data word is formed by packing all the bits of the input data word having the first logic state into a first contiguous set of bit positions in the modified data word and all the bits of the input data word having the second logic state into a second contiguous set of the bit positions in the modified data word. The number of bit positions in the first and second sets is greater than or equal to zero. A result of the Boolean logic tree function is generated based on a pattern of the first and second logic states in the modified data word.

Claims22

Dependent claims

A method of performing a Boolean logic tree function on all bits of a multiple-bit binary input data word having a plurality of bit positions, wherein each bit has one of first and second complementary logic states, the method comprising:

(a) forming a modified data word by packing all the bits of the input data word having the first logic state into a first contiguous set of bit positions in the modified data word and all the bits of the input data word having the second logic state into a second contiguous set of the bit positions in the modified data word, wherein the number of bit positions in the first and second sets is greater than or equal to zero;
and
(b) generating a result of the Boolean logic tree function based on a pattern of the first and second logic states in the modified data word.

A Boolean logic tree reduction circuit for performing a Boolean logic function on all bits of a multiple-bit binary input data word having a plurality of bit positions, wherein each bit has one of first and second complementary logic states, the circuit comprising:

(a) packing means for forming a modified data word by packing all the bits of the input data word having the first logic state into a first contiguous set of bit positions in the modified data word and all the bits of the input data word having the second logic state into a second contiguous set of the bit positions in the modified data word, wherein the number of bit positions in the first and second sets is greater than or equal to zero;
and
(b) means for generating a result of the Boolean logic tree function based on a pattern of the first and second logic states in the modified data word.

Dependencies are inferred from the claim text.

Boolean logic tree reduction circuit

Life of this patent

Boolean logic tree reduction circuit

Life of this patent

Abstract

Claims22