Interleaved VCO with body voltage frequency range control

A phase locked loop (PLL) circuit for generating an output clock signal with a frequency that is a multiple number N times the frequency of a reference clock signal, comprising:

• a voltage controlled oscillator (VCO) generating the output clock signal with a frequency modified in response to a control voltage;
• a frequency divider for frequency dividing the output clock signal by N, generating a frequency divided clock signal;
• a phase frequency detector for comparing the frequency divided clock signal to the reference clock signal and generating a phase/frequency error signal;
• and
• circuitry for converting the phase/frequency error signal to the control voltage, wherein the VCO is a ring oscillator having an input, an output, an odd number M of complementary metal oxide semiconductor (CMOS) inverters series coupled between the input and output, a feedback connection between the input and output, and a number K of voltage controlled feed-forward (FF) stages, each of the K FF stages coupled in parallel with K groups of an odd number of G sequential CMOS inverters selected from the M CMOS inverters, each of the K FF stages having a plurality P channel metal oxide silicon transistors (PFETs) and a plurality of N channel metal oxide silicon transistors (NFETs), at least one of the PFETs having a first isolated region of semiconductor material (body) connected to a first body terminal, and at least one of the NFETs having a second isolated body connected to a second body terminal, wherein the K FF stages are controlled by first and second control voltages coupled to the first and second body terminals respectively,
• wherein each of the K FF stages comprise a CMOS inverter stage coupled in series with a transfer gate stage having a parallel connection of a first PFET and a first NFET, and
• wherein each of the CMOS inverters in the K FF stages comprise a second PFET and a second NFET coupled in series, wherein the second PFET of at least one of the CMOS inverters has a body terminal coupled to the first control voltage by a first clamping circuit preventing a body diode coupled to the body terminal of the second PFET from being forward biased and the second NFET of the at least one of the CMOS inverters has a body terminal coupled to the second control voltage by a second clamping circuit preventing a body diode coupled to the body terminal of the second NFET from being forward biased.

A voltage controlled oscillator (VCO) comprising a ring oscillator having an input, an output, an odd number M of complementary metal oxide semiconductor (CMOS) inverters series coupled between the input and output, a feedback connection between the input and output, and a number K of voltage controlled feed-forward (FF) stages, each of the K FF stages coupled in parallel with K groups of an odd number of G sequential CMOS inverters selected from the M CMOS inverters, each of the K FF stages having a plurality P channel metal oxide silicon transistors (PFETs) and a plurality of N channel metal oxide silicon transistors (NFETs), at least one of the PFETs having a first isolated region of semiconductor material (body) connected to a first body terminal, and at least one of the NFETs having a second isolated body connected to a second body terminal, wherein the K FF stages are controlled by first and second control voltages coupled to the first and second body terminals respectively,

• wherein each of the K FF stages comprises a CMOS inverter stage coupled in series with a transfer gate stage having a parallel connection of a first PFET and a first NFET, and
• wherein each of M CMOS inverters comprise a second PFET and a second NFET coupled in series, wherein the second PFET of at least one of the CMOS inverters has a body terminal coupled to the first control voltage by a first clamping circuit preventing a body diode coupled to the body terminal of the second PFET from being forward biased and the second NFET of the at least one of the CMOS inverters has a body terminal coupled to the second control voltage by a second clamping circuit preventing a body diode coupled to the body terminal of the second NFET from being forward biased.

A phase locked loop (PLL) circuit for generating an output clock signal with a frequency that is a multiple number N times the frequency of a reference clock signal, comprising:

• a voltage controlled oscillator (VCO) generating the output clock signal with a frequency modified in response to a control voltage;
• a frequency divider for frequency dividing the output clock signal by N, generating a frequency divided clock signal;
• a phase frequency detector for comparing the frequency divided clock signal to the reference clock signal and generating a phase/frequency error signal;
• and
• circuitry for converting the phase/frequency error signal to the control voltage, the VCO is configured as a ring oscillator having an input, an output, an odd number M of complementary metal oxide semiconductor (CMOS) inverters series coupled between the input and output, a feedback connection between the input and output, and a number K of voltage controlled feed-forward (FF) stages, each of the K FF stages coupled in parallel with K groups of an odd number of G sequential CMOS inverters selected from the M CMOS inverters, each of the K FF stages having a plurality P channel metal oxide silicon transistors (PFETs) and a plurality of N channel metal oxide silicon transistors (NFETs), at least one of the PFETs having a first isolated region of semiconductor material (body) connected to a first body terminal, and at least one of the NFETs having a second isolated body connected to a second body terminal, wherein the K FF stages are controlled by first and second control voltages coupled to the first and second body terminals respectively,
• wherein each of the K FF stages comprise a CMOS inverter stage coupled in series with a transfer gate stage having a parallel connection of a first PFET and a first NFET,
• wherein the first PFET of the transfer gate stage has a body terminal coupled to the first control voltage and the NFET of the transfer gate has a body terminal coupled to the second control voltage, and
• wherein each of the CMOS inverters in the K FF stages comprise a second PFET and a second NFET coupled in series, wherein the second PFET of at least one of the CMOS inverters has a body terminal coupled to the first control voltage by a first clamping circuit preventing a body diode coupled to the body terminal of the second PFET from being forward biased and the second NFET of the at least one of the CMOS inverters has a body terminal coupled to the second control voltage by a second clamping circuit preventing a body diode coupled to the body terminal of the second NFET from being forward biased.