Metal programmable phase-locked loop

A phase-locked loop (PLL) cell for fabrication on an integrated circuit, the cell definition comprising:

• a first PLL configuration formed by a first plurality of subcells, wherein each of the first plurality of subcells comprises a base layer pattern and a metallization pattern;
• and
• a second PLL configuration formed by a second plurality of subcells, wherein at least one of the second plurality of subcells is common with a corresponding one of the first plurality of subcells and has the same base layer pattern and the same metallization pattern, wherein at least another one of the second plurality of subcells is common with a corresponding one of the first plurality of subcells and has the same base layer pattern and a different metallization pattern, and wherein the second plurality of subcells further comprises at least one subcell that has a different base layer pattern and a different metallization pattern than a corresponding one of the first plurality of subcells.

A phase-locked loop within an integrated circuit assembly, the phase-locked loop comprising:

• a plurality of subcells of semiconductor devices arranged in a base layer pattern on base layers of the integrated circuit assembly, wherein the plurality of subcells comprises a loop filter subcell, which comprises a plurality of loop filter capacitors;
• and
• one or more metal layers formed over and interconnecting the plurality of semiconductor devices in a metallization pattern, which operatively couples a selected number of the loop filter capacitors into the phase-locked loop and operatively decouples any remaining ones of the loop filter capacitors out of the phase-locked loop such that the loop filter has an effective capacitance that is selectable with the metallization pattern, wherein the phase-locked loop has an output frequency range that is changeable with a change to the metallization pattern without a corresponding change to the base layer pattern.

A phase-locked loop within an integrated circuit assembly, the phase-locked loop comprising:

• a plurality of subcells of semiconductor devices arranged in a base layer pattern on base layers of the integrated circuit assembly, wherein the plurality of subcells comprises a clock buffer subcell, which drives a clock output from the phase-locked loop;
• and
• one or more metal layers formed over and interconnecting the plurality of semiconductor devices in a metallization pattern, wherein the clock buffer subcell comprises a plurality of clock buffer circuit configurations, which are selectable with the metallization pattern, and wherein the phase-locked loop has an output frequency range that is changeable with a change to the metallization pattern without a corresponding change to the base layer pattern.