Control signal generation for a low jitter switched-capacitor frequency synthesizer
AssigneeLattice Semiconductor Corporation
InventorsXiang Zhu, Ming Qu, Zhengyu Yuan
Life of this patent
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Abstract
A phase detector and control signal generator responds to a reference signal and a feedback signal to produce a non-delayed up and down signal. A programmable delay unit delays the non-delayed up and down signal to provide up and down signals for a charge pump. A divider configured to respond to the up and down signals provides a divided clock signal. A non-overlapped clock generator configured to respond to the divided clock signal to provide non-overlapped hold even and hold odd signals for the switched-capacitor ripple-smoothing filter.
Claims16
A control signal generator for a switched-capacitor ripple-smoothing filter, comprising:
- a phase detector configured to compare the phases of a reference signal and a feedback signal and generate a non-delayed up signal and a non-delayed down signal responsive to the phase comparison;
- a programmable delay circuit configured to delay the non-delayed up and down signals to provide an up signal and a down signal;
- a divider circuit configured to respond to the up and down signals to provide a divided clock signal;
- and
- a non-overlapped clock generator configured to respond to the divided clock signal to provide non-overlapped hold even and hold odd signals.
A method of generating control signals for a switched-capacitor ripple-smoothing filter, comprising:
- programmably delaying a periodically-pulsed non-delayed up signal and a periodically-pulsed non-delayed down signal to provide a periodically-pulsed up and down signal;
- asserting a timing signal from the end of each up and down pulse cycle to the end of the subsequent up and down pulse cycle;
- processing the timing signal to generate a non-overlapped hold even signal and a hold odd signal, and
- processing the timing signal and the non-delayed up signal and the non-delayed down signals to provide a non-overlapped reset signal.
A control signal generator for a switched-capacitor ripple-smoothing filter, comprising:
- a phase detector configured to compare the phases of a reference signal and a feedback signal and generate an up signal and a down signal responsive to the phase comparison;
- a programmable delay circuit configured to delay the up and down signals;
- a divider circuit configured to respond to the programmably delayed up and down signals to provide a divided clock signal;
- and
- a clock generator configured to respond to the divided clock signal to provide hold even and hold odd signals.
Dependencies are inferred from the claim text.