Voltage buffer for capacitive loads

A circuit to supply a set of output voltages from a respective set of input voltage, comprising:

• a plurality of N first transistors connected in series between a first of a voltage source and a reference voltage and, through a current limiting circuit, a second of the voltage source and the reference voltage;
• a plurality of N second transistors connected in series and connected in parallel with the first transistors between the first of the voltage source and the reference voltage and, through said current limiting circuit, the second of thie voltage source and the reference voltage;
• and
• a plurality of N differential gain stages each having a first input connected to receive a respective one of the input voltage, a second input connected to a node at the terminal on the current limiting circuit side of a respective one of the first transistors, and an output connected to the control gate of the respective one of the first transistors and a respective one of the second transistors, wherein the respective output voltage is supplied from a node at the terminal on the current limiting circuit side of the second transistor.

A circuit to supply a set of output voltages from a respective set of input voltage, comprising:

• a plurality of N first transistors connected in series between a first of a voltage source and a reference voltage and, through a current limiting circuit, a second of the voltage source and the reference voltage;
• a plurality of N second transistors connected in series and connected in parallel with the first transistors between the first of the voltage source and the reference voltage and, through said current limiting circuit, the second of the voltage source and the reference voltage;
• and
• a plurality of N differential gain stages each having a first input connected to receive a respective one of the input voltage, a second input connected to a node at the terminal on the current limiting circuits side of a respective one of the first transistors, and an output connected to the control gate of the respective one of the first transistors and a respective one of the second transistors, wherein the respective output voltage is supplied from a node at the terminal on the current limiting circuit side of the second transistor.