Input circuits including boosted voltage and related methods

An input circuit for an integrated circuit device, the input circuit comprising:

• a boosting circuit configured to receive a supply voltage of the integrated circuit device and to generate a boosted voltage higher than the supply voltage;
• a protection circuit configured to receive an input signal and the boosted voltage and to generate an output signal that changes responsive to changes in the input signal;
• and
• a buffer circuit configured to generate a buffered output signal responsive to the output signal generated by the protection circuit;
• wherein the boosting circuit includes a supply voltage boosting circuit configured to boost a level of the supply voltage and a supply voltage dropping circuit configured to drop a level of the supply voltage.

An input circuit for an integrated circuit device, the input circuit comprising:

• a boosting circuit configured to receive a supply voltage of the integrated circuit device and to generate a boosted voltage higher than the supply voltage;
• a protection circuit configured to receive an input signal and the boosted voltage and to generate an output signal that changes responsive to changes in the input signal;
• and
• a buffer circuit configured to generate a buffered output signal responsive to the output signal generated by the protection circuit;
• wherein the boosting circuit comprises,
• a first PMOS transistor electrically coupled in series with a first NMOS transistor between the supply voltage and an output of the boosting circuit wherein the first NMOS transistor is between the first PMOS transistor and the supply voltage,
• a second PMOS transistor electrically coupled in series with a second NMOS transistor between the supply voltage and an output of the boosting circuit wherein the second NMOS transistor is between the second PMOS transistor and the supply voltage,
• a first capacitor coupled to a bulk of the first and second PMOS transistors,
• a second capacitor coupled to a source terminal of the first NMOS transistor and to a gate terminal of the second NMOS transistor,
• a third capacitor coupled to a source terminal of the second NMOS transistor and to a gate terminal of the first NMOS transistor, and
• a fourth capacitor coupled to the output of the boosting circuit.

A method of receiving an input signal for an integrated circuit device, the method comprising:

• generating a boosted voltage responsive to a supply voltage of the integrated circuit device wherein the boosted voltage is higher than the supply voltage;
• generating an output signal responsive to the boosted voltage and the input signal wherein the output signal changes responsive to changes in the input signal wherein generating the output signal comprises generating a logic high voltage level output responsive to a logic high voltage level of the input signal wherein the logic high voltage level output is less than the logic high voltage level of the input signal and generating a logic low voltage level output responsive to a logic low voltage level of the input signal;
• and
• generating a buffered output signal responsive to the output signal wherein a logic high voltage level of the buffered output signal is less than a logic high voltage level of the input signal.