US 7,002,397 B2Granted

Method of setting back bias of MOS circuit, and MOS integrated circuit

AssigneeRenesas Technology Corp.

InventorsMasaharu Kubo, Mitsuru Hiraki, Hiroyuki Mizuno, Syuji Ikeda

Life of this patent

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Abstract

In a MOS circuit comprising a plurality of MOSFETs constituting a digital circuit, an input signal is supplied to the digital circuit, and a first back bias voltage is supplied to a semiconductor substrate or a semiconductor well region in which the MOSFETs are formed, so that a pn junction between the semiconductor substrate or the semiconductor well region and a source region is brought to a forward voltage. In a non-operating state in which a circuit operation is suspended by the input signal supplied to the digital circuit as a fixed level, a second back bias voltage is applied to the semiconductor substrate or the semiconductor well region so that the pn junction between the semiconductor substrate or the semiconductor well region and the source region is brought to a reverse voltage.

Claims3

Dependent claims

A semiconductor integrated circuit including a plurality of operation modes, comprising:

a plurality of circuit blocks, each comprising a plurality of P channel MOS transistors, and a plurality of N channel MOS transistors,
wherein said plurality of circuit blocks include a first circuit block and a second circuit block,
wherein said operation modes include a first mode and a second mode,
wherein said N channel MOS transistors included in said first circuit block are provided a bias voltage higher than a ground voltage in said first mode, and are provided a bias voltage lower than said ground voltage in said second mode,
wherein said P channel MOS transistors included in said first circuit block are provided a bias voltage lower than a power supply voltage in said first mode, and are provided a bias voltage higher than said power supply voltage in said second mode,
wherein said N channel MOS transistors included in said second circuit block are provided a bias voltage lower than said ground voltage in said second mode,
wherein said P channel MOS transistors included in said second circuit block are provided a bias voltage higher than said power supply voltage in said second mode,
wherein said N channel MOS transistors included in said second circuit block are provided a bias voltage equal to said ground voltage in said first mode, and
wherein said P channel MOS transistors included in said second circuit block are provided a bias voltage equal to said power supply voltage in said first mode.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/401,734Filed 31 Mar 2003 · continuation
Priority: JP 11-01746026 Jan 1999
Published: US 2003/0218494 A127 Nov 2003
Granted: 21 Feb 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 84/859
Complementary IGFETs, e.g. CMOS: comprising both N-type and P-type wells, e.g. twin-tub
H10D 86/201
Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless…
H10W 10/031
Manufacture or treatment: of isolation regions comprising PN junctions
H10W 10/30
Isolation regions in semiconductor bodies between components of integrated devices: isolation regions comprising PN junctions