Frequency converter

A frequency converter comprising:

• a first transistor pair having a first transistor and a second transistor respectively having first terminals commonly connected to each other as a first common terminal of said first transistor pair and second terminals commonly connected to each other as a second common terminal of said first transistor pair, the commonly-connected first terminals being connected to a power supply terminal by way of a first passive element;
• a third transistor having a first terminal directly or indirectly connected to said power supply terminal, and a second terminal connected to the commonly-connected second terminals of said first and second transistors of said first transistor pair;
• a second passive element having an end connected to the second common terminal of said first transistor pair, and another end directly or indirectly grounded;
• a first output terminal connected to the first common terminal of said first transistor pair;
• a second transistor pair having a fourth transistor and a fifth transistor respectively having first terminals commonly connected to each other as a first common terminal of said second transistor pair and second terminals commonly connected to each other as a second common terminal of said second transistor pair, the commonly-connected first terminals being connected to said power supply terminal by way of a third passive element;
• a sixth transistor having a first terminal directly or indirectly connected to said power supply terminal, and a second terminal connected to the commonly-connected second terminals of said fourth and fifth transistors of said second transistor pair;
• a fourth passive element having an end connected to the second common terminal of said second transistor pair, and another end directly or indirectly grounded;
• and
• a second output terminal connected to the first common terminal of said second transistor pair, a first signal being applied to third terminals of said first and fifth transistors, a second signal having a phase opposite to that of the first signal being applied to third terminals of said second and fourth transistors, a third signal being applied to the second common terminal of said first transistor pair, a fourth signal having a phase opposite to that of the third signal being applied to the second common terminal of said second transistor pair, and a reference signal being applied to third terminals of said third and sixth transistors.