US 7,002,390 B2 · Delay matching for clock distribution in a logic circuit

Abstract

Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an original signal, such as a clock signal, to be redistributed. In general, the delay matching circuit may include a propagation gate multiplexer have a particular configuration. The delay matching circuit imposes a delay substantially equal to the clock-to-Q delay experienced by divided versions of the original signal. In this manner, the delay matching circuit ensures that the rising and falling edges of the original signal and the divided signal are in substantial alignment, enabling synchronous operation. Hence, the delay matching circuit is capable of synchronizing the redistributed and divided signals.

Claims24

Dependent claims

A clock distribution circuit comprising:

a clock source to generate a clock signal;
a clock divider to divide the clock signal and produce a divided clock signal, and including a flip-flop that introduces a clock-to-Q propagation delay to the divided clock signal;
and
a delay matching circuit to distribute the clock signal, and to introduce a second propagation delay to the clock signal, the second propagation delay substantially matching the clock-to-Q propagation delay introduced in the divided clock signal by the flip-flop, the delay matching circuit comprising a plurality of components configured to substantially mimic a corresponding plurality of components in the flip-flop.

1 more element

Dependencies are inferred from the claim text.

Delay matching for clock distribution in a logic circuit

Life of this patent

Delay matching for clock distribution in a logic circuit

Life of this patent

Abstract

Claims24