Fast static receiver with input transition dependent inversion threshold
AssigneeIntel Corporation
InventorsAtila Alvandpour, Ram Krishnamurthy
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Abstract
A static receiver having a first inversion threshold for received signals undergoing a HIGH-to-LOW transition, and a second inversion threshold for received signals undergoing a LOW-to-HIGH transition, where the first inversion threshold is greater than the second inversion threshold. One embodiment comprises a static receiver, a pFET, and a nFET, where when a HIGH-to-LOW transition is being received at the receiver's input port, the pFET is coupled to the input port so as to contribute to raising the inversion threshold, and when a LOW-to-HIGH transition is being received at the input port, the nFET is coupled to the input port so as to contribute to lowering the inversion threshold. Other embodiments are described and claimed.
Claims13
A receiver comprising:
- a first inverter comprising an input port having an input voltage and an output port;
- a pFET comprising a gate and a drain connected to the output port;
- an nFET comprising a gate and a drain connected to the output port;
- a first transmission gate to couple the gate of the pFET to the input port;
- and
- a second transmission gate to couple the gate of the nFET to the input port;
- wherein the receiver has a first inversion threshold for the input voltage transitioning from HIGH to LOW, and a second inversion threshold for the input voltage transitioning from LOW to HIGH, where the first inversion threshold is greater than the second inversion threshold.
A receiver comprising:
- a first inverter comprising an input port having an input voltage and an output port;
- a pFET comprising a gate and a drain connected to the output port;
- an nFET comprising a gate and a drain connected to the output port;
- a first transmission gate;
- a second transmission gate;
- and
- wherein when the input voltage is transitioning from HIGH to LOW, the first transmission gate is ON to provide a low impedance path between the gate of the pFET and the input port, and the second transmission gate is OFF to provide a high impedance path between the gate of the nFET and the input port;
- and when the input voltage is transitioning from LOW to HIGH, the second transmission gate is ON to provide a low impedance path between the gate of the nFET and the input port, and the first transmission gate is OFF to provide a high impedance path between the gate of the pFET and the input port.
A computer system comprising:
- memory;
- a die in communication with the memory, the memory not residing on the die, the die comprising a receiver, the receiver comprising:
- a first inverter comprising an input port having an input voltage and an output port;
- a pFET comprising a gate and a drain connected to the output port;
- an nFET comprising a gate and a drain connected to the output port;
- a first transmission gate to couple the gate of the pFET to the input port;
- and
- a second transmission gate to couple the gate of the nFET to the input port;
- wherein the receiver has a first inversion threshold for the input voltage transitioning from HIGH to LOW, and a second inversion threshold for the input voltage transitioning from LOW to HIGH, where the first inversion threshold is greater than the second inversion threshold.
Dependencies are inferred from the claim text.