Self-limiting pulse width modulation regulator
AssigneeAtmel Corporation
InventorAlbert S. Weiner
Life of this patent
Estimating the term…
Abstract
A self-adjusting PWM regulator which minimizes undershoot and overshoot conditions is disclosed. The regulator includes a charge pump, a voltage comparator circuit, and a latch circuit. The input of the voltage comparator circuit includes an output of the charge pump. The input of the latch circuit includes an output from the voltage comparator circuit. The latch circuit includes a pair of SR latches coupled to a pair of AND/OR gates. The latch circuit transmits a first signal to the charge pump to prevent an overshoot condition if the output from the voltage comparator circuit is in a first state, and transmits a second signal to prevent an undershoot condition if the output from the voltage comparator circuit is in a second state. This keeps the charge pump adjusted within the limits of its control.
Claims13
A pulse width modulation regulator, comprising:
- a first controller, wherein the first controller receives as input a clock signal and a first control signal and outputs a first pulse width modulator signal and a first enable signal;
- a second controller, wherein the second controller receives as input an inverse of the clock signal and a second control signal and outputs a second pulse width modulated signal and a second enable signal;
- wherein the first enable signal maintains the second pulse width modulated signal at first state when the first pulse width modulated signal has not increased to a desired pulse width,
- wherein the second enable signal maintains the first pulse width modulated signal at a second state when the second pulse width modulated signal has not decreased to the desired pulse width;
- and
- an OR gate for receiving as input the first and second pulse width modulated signals and for providing an output signal.
A pulse width modulation regulator, comprising:
- a first controller, wherein the first controller receives as input a clock signal and a first control signal and outputs a first pulse width modulator signal and a first enable signal;
- a second controller, wherein the second controller receives as input an inverse of the clock signal and a second control signal and outputs a second pulse width modulated signal and a second enable signal;
- wherein the first enable signal maintains the second pulse width modulated signal at first state when the first pulse width modulated signal has not increased to a desired pulse width,
- wherein the second enable signal maintains the first pulse width modulated signal at a second state when the second pulse width modulated signal has not decreased to the desired pulse width;
- and
- an OR gate for receiving as input the first and second pulse width modulated signals and for providing an output signal,
- wherein at least the first or the second controller comprises:
- a charge pump;
- a comparator circuit coupled to the charge pump, the comparator circuit for providing a pulse width modulated signal;
- and
- a latch circuit coupled to the charge pump for ensuring that the charge pump is adjusted such that an undershoot condition and an overshoot condition of the pulse width modulated signal is minimized.
Dependencies are inferred from the claim text.