Phase locked loop circuit

A phase locked loop circuit comprising:

• a phase comparator for receiving a reference clock signal REF and a clock signal CLK and for comparing a phase of the reference clock signal REF with a phase of the clock signal CLK so as to output a phase difference signal which depends on a phase difference Δφ between the reference clock signal REF and the clock signal CLK;
• a charge-pump circuit for producing an output current Io which depends on the phase difference signal;
• a loop filter for converting the output current Io into an output voltage;
• a voltage controlled oscillator for generating a signal having a frequency fo which depends on the output voltage as a clock signal CLK′;
• and
• a 1/N divider for dividing the frequency fo of the clock signal CLK′ by N, where N is an arbitrary natural number, so as to supply a signal having a frequency fo/N as the clock signal CLK to the phase comparator,
• wherein the phase comparator and the charge-pump circuit are configured to satisfy a relationship of Kp2>Kp1 in an Io−Δφ characteristic, where Kp1 indicates a slope Kp in the case where |Δφ|>Δφo, Kp2 indicates a slope Kp in the case where |Δφ|≦Δφo, Kp being defined by Kp=dIo/dΔφ, and Δφo being a constant indicating a predetermined phase error.