I/O circuit using low voltage transistors which can tolerate high voltages even when power supplies are powered off

Abstract

An apparatus for providing bias voltages for input/output (I/O) connections on low voltage integrated circuits. In one embodiment, the invention comprises an I/O pad, a pull-down transistor device that has a protective transistor coupled to said I/O pad, and a pull-up transistor device that has a second protective transistor, coupled to said I/O pad. A first switch coupled to the first protective transistor is responsive to a first supply voltage, a second supply voltage, and a reference voltage. Likewise, a second switch coupled to the second protective transistor is responsive to the first supply voltage and the reference voltage. A first self-bias circuit is also coupled to the first switch, wherein said the self-bias circuit uses a voltage at said I/O pad to bias the first protective transistor when both of the first and second supply voltages are powered off. Likewise, a second self-bias circuit coupled to the second switch, wherein the second self-bias circuit also uses the voltage at the I/O pad and an output of the first self bias circuit, to bias the second protective transistor when the first supply voltage is powered off.

Dependencies are inferred from the claim text.