Phase detector for a programmable clock synchronizer
AssigneeHewlett-Packard Development Company, L.P.
InventorRichard W. Adkisson
Life of this patent
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Abstract
A phase detector in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain that is clocked with a first clock signal and second circuitry disposed in a second clock domain that is clocked with a second clock signal. The phase detector includes means for sampling the second clock signal with the first clock signal to generate a sampled clock signal. By tracking movement in a predetermined transition in the sampled clock signal, the phase detector is operable to determine the phase difference between the first and second clock signals.
Claims20
A phase detector operable in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, comprising:
- at least one flip flop operable to sample said second clock signal with said first clock signal, said at least one flip flop thereby operating to generate a predetermined transition in a sampled clock signal following coincident edges between said first and second clock signals;
- and
- a detector for detecting a movement in said predetermined transition, said movement being indicative of a phase difference between said first and second clock signals.
A phase detection method operable in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, comprising:
- sampling said second clock signal with said first clock signal to generate a sampled clock signal;
- and
- detecting a phase difference between said first clock signal and said second clock signal by tracking movement in a predetermined transition in said sampled clock signal.
A phase detector operable in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, comprising:
- means for sampling said second clock signal with said first clock signal to generate a sampled clock signal;
- and
- means for detecting a phase difference between said first clock signal and said second clock signal by tracking movement in a predetermined transition in said sampled clock signal.
Dependencies are inferred from the claim text.