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US 7,002,375 B2Granted
Robust variable keeper strength process-compensated dynamic circuit and method
AssigneeIntel Corporation
InventorsSteven K. Hsu, Ram Krishnamurthy, Chris Hyung-il Kim
Life of this patent
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Abstract
A variable keeper strength based process-compensated dynamic circuit and method provides a robust digital way to overcome the intrinsic parameter variation present in manufactured die. Using a process-compensated dynamic circuit, the wide robustness and delay distribution becomes narrower which improves performance without sacrificing worst-case robustness. The strength of the keeper is programmed depending on the amount of die leakage. The keeper will have an optimal strength for the best and worst case leakage, allowing better performance with improved worst-case robustness.
Claims36
A programmable keeper, comprising:
- a keeper circuit;
- and
- a controller to generate a digital control signal for automatically adjusting a strength of the keeper circuit in response to a signal indicative of leakage current, the keeper circuit including at least a first keeper of a first size and a second keeper of a second size, and the controller selectively activating the first keeper and the second keeper using the digital control signal to adjust the strength of the digital keeper, the controller controlling activation of the first keeper based on at least a first bit of the digital control signal and controlling activation of the second keeper based on at least a second bit of the digital control signal.
A programmable keeper, comprising:
- a keeper circuit;
- and
- a controller to generate a digital control signal for automatically adjustinng a strength of the keeper circuit in response to a signal indicative of leakage current, the keeper circuit including N keepers of predetermined sizes with N being an integer greater than 1, and the controller generating N bit signals to control activation of respective ones of the N keepers to adjust the strength of the keeper circuit.
A dynamic logic circuit, comprising:
- a logic gate having a node;
- and
- a programmable digital keeper which controls a voltage at the node of the logic gate, said digital keeper including:
- (a) N keeper circuits of predetermined sizes with N being an integer, and
- (b) a controller for automatically adjusting a strength of the digital keeper based on a signal indicative of leakage current, the controller adjusting the strength of the digital keeper by selectively activating the N keeper circuits.
2 more elements
A processing system, comprising:
- a dynamic logic circuit having a node;
- and
- a programmable digital keeper which controls a voltage at the node of the dynamic logic circuit, said programmable digital keeper including:
- (a) N keeper circuits of predetermined sizes with N being an integer, and
- (b) a controller for automatically adjusting a strength of the digital keeper based on a signal indicative of leakage current, the controller adjusting the strength of the digital keeper by generating N bit signals to selectively activate respective ones of the N keeper circuits.
2 more elements
A programmable keeper, comprising:
- a keeper circuit;
- a controller to generate a digital control signal for automatically adjusting a strength of the keeper circuit in response to a signal indicative of leakage current;
- and
- a detector, coupled to the controller, to generate the signal indicative of the leakage current.
1 more element
A programmable keeper, comprising:
- a keeper circuit;
- and
- a controller to generate a digital control signal for automatically adjusting a strength of the keeper circuit in response to a signal indicative of leakage current, wherein the keeper circuit includes a plurality of keepers having different binary weights, and wherein the digital control signal selects different combinations of the binary-weighted keepers to achieve different strengths of the keeper circuit.
A dynamic logic circuit, comprising:
- a logic gate having a node;
- and
- a programmable digital keeper to control a voltage at the node of the logic gate, the digital keeper including:
- (a) a keeper circuit, and
- (b) a controller to automatically adjust a strength of the keeper circuit based on a signal indicative of leakage current
- a detector, coupled to the controller, to generate the signal indicative of the leakage current.
3 more elements
A dynamic logic circuit, comprising:
- a logic gate having a node;
- and
- a programmable digital keeper which controls a voltage at the node of the logic gate, the digital keeper including:
- (a) a digital keeper circuit, and
- (b) a controller to automatically adjust a strength of the digital keeper circuit based on a signal indicative of leakage current, wherein the digital keeper circuit includes a plurality of keepers having different binary weights, and wherein the digital control signal selects different combinations of the binary-weighted keepers to achieve different strengths of the digital keeper circuit.
2 more elements
A processing system, comprising:
- a dynamic logic circuit having a node;
- and
- a programmable digital keeper which controls a voltage at the node of the dynamic logic circuit, the digital keeper including:
- (a) a keeper circuit, and
- (b) a controller to automatically adjust a strength of the keeper circuit based on a signal indicative of leakage current, wherein the keeper circuit includes a plurality of keepers having different binary weights, and wherein the digital control signal selects different combinations of the binary-weighted keepers to achieve different strengths of the keeper circuit.
2 more elements
Dependencies are inferred from the claim text.