Domino logic compatible scannable flip-flop
AssigneeSTMicroelectronics S.r.l.
InventorsScott B. Anderson, Razak Hossain, Thomas D. Zounes
Life of this patent
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Abstract
A testable, prechargeable circuit has a driving circuit for producing a driving circuit output signal. A timing circuit receives a clock signal and the driving circuit output signal to cause an output of the testable, prechargeable circuit to be in a low state when the clock signal is low. The timing circuit also causes the output of the circuit to be timed with a state change in the clock signal to provide a domino logic output signal. Either a data signal or a test signal are multiplexed to the input of the driving circuit to produce respectively the domino logic output signal or a test output signal. A static logic circuit receives the test output signal to produce a test signal output.
Claims20
A circuit comprising:
- a driving circuit for producing a driving circuit output signal;
- an input circuit for selectively applying a data signal and a test signal to an input of the driving circuit;
- and
- a sequential timing circuit operable to receive said driving circuit output signal and a clock signal having first and second states, to cause an output of said sequential timing circuit to be in a low state when said clock signal is in said first state, and to cause the output of the sequential timing circuit to be timed with a state change in said clock signal from said first state to said second state and to represent said driving circuit output signal.
A logic circuit, comprising:
- a domino logic circuit having a logic signal input and a logic signal output;
- a circuit for timing said logic signal output with a clock transition;
- a circuit to selectively apply a data signal and a test signal to said logic signal input to produce respectively a domino logic output signal and a test output signal;
- and
- a static logic circuit to receive said logic signal output to produce a test signal output.
A latch circuit, comprising:
- a master latch circuit clocked by a clock signal;
- a slave latch circuit also clocked by said clock signal;
- and
- a timing element that operates to cause an output of said master latch to be in a low state when said clock signal is in a low state and to cause said output of said master latch to be a master latch output when said clock signal transitions to a high state.
Dependencies are inferred from the claim text.