Moderate current 5V tolerant buffer using a 2.5 volt power supply

A method of providing a low voltage, 5V tolerant buffer, comprising:

• providing a series connection of at least three transistors;
• connecting an end of an upper transistor in said series connection to a PAD;
• connecting an end of a lower transistor of said series connection to ground;
• providing a bias voltage to a gate of said upper transistor, said bias voltage being based on a difference between a power supply voltage and a voltage at said PAD;
• providing a power supply input to a gate of a central one of said series connection of three transistors;
• and
• providing an input stage adapted to be driven by a node between said central transistor and said lower transistor.

Apparatus for providing a low voltage, 5V tolerant buffer, comprising:

• means for inverting an input signal to a series connection of an upper transistor, a central transistor, and a lower transistor;
• means for connecting a terminal of said upper transistor to a PAD;
• means for connecting a terminal of said lower transistor to ground;
• means for providing a bias voltage to a gate of said upper transistor, said bias voltage being based on a difference between a power supply voltage and a voltage at said PAD;
• and
• means for coupling a power supply input to a gate of said central transistor;
• and
• means for providing an input stage adapted to be driven by a node between a central transistor and said lower transistor;
• wherein said buffer is a bi-directional buffer.

A low voltage, 5V tolerant buffer, comprising:

• a series connection of at least three transistors, a terminal of an upper transistor in said series connection being connected to a PAD, and a terminal of a lower transistor of said series connection being connected to ground;
• and
• a bias generator, an output of said bias generator being connected to a gate of said upper transistor;
• wherein a gate of a central one of said series connection of three transistors is adapted to be connected to a power supply of no greater than 2.5V nominal;
• and
• wherein said bias generator comprises a series connection of two transistors between said power supply and said PAD.

A low voltage, 5V tolerant buffer, comprising:

• a series connection of at least three transistors, a terminal of an upper transistor in said series connection being connected to a PAD, and a terminal of a lower transistor of said series connection being connected to ground;
• and
• a bias generator, an output of said bias generator being connected to a gate of said upper transistor, said bias generator comprising:
• a series connection of two p-channel field effect transistors, a gate of one of said two transistors is adapted to be coupled to said PAD, and a gate of the other of said two transistors is adapted to be driven by said power supply, and
• said series connection of said two transistors being connected between said power supply and said PAD;
• wherein a gate of a central one of said series connection of three transistors is adapted to be connected to a power supply of no greater than 2.5V nominal.